专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06505260B2 Computer system with adaptive memory arbitration scheme 失效
标题翻译：具有自适应内存仲裁方案的计算机系统
公开(公告)号：US06505260B2
公开(公告)日：2003-01-07
申请号：US09784690
申请日：2001-02-15
申请人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
发明人： Kenneth T. Chin , C. Kevin Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
摘要翻译：计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。这样的方案可防止低优先级的设备变得“记忆不足”。因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务最迫切的要求。此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

2. 发明授权

US06286083B1 Computer system with adaptive memory arbitration scheme 失效
标题翻译：具有自适应内存仲裁方案的计算机系统
公开(公告)号：US06286083B1
公开(公告)日：2001-09-04
申请号：US09112000
申请日：1998-07-08
申请人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
发明人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , Michael J. Collins , C. Kevin Coffee
IPC分类号： G06F1318
CPC分类号： G06F13/1605
摘要： A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests. Also, the adaptive memory arbitration scheme introduces a flexible method of adjustable priority-weighting which permits selected devices to transact a programmable number of consecutive memory accesses without those devices losing request priority.
摘要翻译：计算机系统包括用于对存储器访问请求进行优先级的自适应存储器仲裁器，包括自调整可编程请求优先级排序系统。存储器仲裁器在每个仲裁周期内进行调整，从而降低获取内存仲裁的任何请求的优先级。因此，初始保持低优先级排序的存储器请求可以逐渐提前优先，直到该请求赢得存储器仲裁。这样的方案可防止低优先级的设备变得“记忆不足”。因为某些类型的存储器请求（例如刷新请求和存储器读取）固有地需要比其他请求（诸如存储器写入）更快的存储器访问，所以自适应存储器仲裁器另外将不可调整的优先级结构集成到自适应排名系统中，从而保证更快的服务最迫切的要求。此外，自适应存储器仲裁方案引入了可调整优先权重的灵活方法，其允许所选择的设备在没有丢失请求优先级的情况下处理可编程数量的连续存储器访问。

3. 发明授权

US06279065B1 Computer system with improved memory access 失效
标题翻译：具有改进的存储器访问的计算机系统
公开(公告)号：US06279065B1
公开(公告)日：2001-08-21
申请号：US09090271
申请日：1998-06-03
申请人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , C. Kevin Coffee , Michael J. Collins
发明人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , C. Kevin Coffee , Michael J. Collins
IPC分类号： G06F1338
CPC分类号： G06F13/4239 , G06F13/4059
摘要： A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.
摘要翻译：计算机系统包括CPU和由桥逻辑单元耦合的存储器件。 CPU到存储器写入请求（包括要写入的数据）暂时存储在桥逻辑单元的队列中。在所有写入数据已经被存储在队列中并且可用于存储器装置之前，桥逻辑单元优选地开始到存储器装置的写周期。通过尽早开始内存循环，减少了将所有写数据存储在队列中，然后从队列中取消队列数据所需的总时间。因此，许多CPU到存储器写入事务被更有效地执行，并且通常以比先前可能的更少的延迟来执行。

4. 发明授权

US06247102B1 Computer system employing memory controller and bridge interface permitting concurrent operation 失效
标题翻译：采用内存控制器和桥接口的计算机系统允许并行运行
公开(公告)号：US06247102B1
公开(公告)日：2001-06-12
申请号：US09047876
申请日：1998-03-25
申请人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , C. Kevin Coffee , Michael J. Collins , John Larson
发明人： Kenneth T. Chin , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo , Jeffrey C. Stevens , C. Kevin Coffee , Michael J. Collins , John Larson
IPC分类号： G06F1314
CPC分类号： G06F13/1642 , G06F13/4036
摘要： A computer system includes a CPU, a memory device, two expansion buses, and a bridge logic unit coupling together the CPU, the memory device and the expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. The bridge logic unit generally routes bus cycle requests from one of the four buses to another of the buses while concurrently routing bus cycle requests to another pair of buses. The bridge logic unit preferably includes four interfaces, one each to the CPU, memory device and the two expansion buses. Each pair of interfaces are coupled by at least one queue; write requests are stored (or “posted”) in write queues and read data are stored in read queues. Because each interface can communicate concurrently with all other interfaces via the read and write queues, the possibility exists that a first interface cannot access a second interface because the second interface is busy processing read or write requests from a third interface, thus starving the first interface for access to the second interface. To remedy this starvation problem, the bridge logic unit prevents the third interface from posting additional write requests to its write queue, thereby permitting the first interface access to the second interface. Further, read cycles may be retried from one interface to allow another interface to complete its bus transactions.
摘要翻译：计算机系统包括CPU，存储器件，两个扩展总线以及将CPU，存储器件和扩展总线耦合在一起的桥逻辑单元。 CPU通过CPU总线耦合到桥逻辑单元，存储器件通过存储器总线耦合到桥逻辑单元。桥接逻辑单元通常将总线周期请求从四条总线之一路由到另一条总线，同时将总线周期请求转发到另一对总线。桥逻辑单元优选地包括四个接口，每个接口连接到CPU，存储设备和两个扩展总线。每对接口由至少一个队列耦合; 写入请求在写入队列中被存储（或“发布”），并且读取数据被存储在读取队列中。因为每个接口可以通过读写队列与所有其他接口同时进行通信，所以存在第一接口无法访问第二接口的可能性，因为第二接口正忙于处理来自第三接口的读或写请求，从而使第一接口用于访问第二个接口。为了解决这个饥饿问题，桥接逻辑单元防止第三接口向其写入队列发布额外的写入请求，从而允许第一接口访问第二接口。此外，可以从一个接口重试读周期，以允许另一接口完成其总线事务。

5. 发明授权

US06216190B1 System and method for optimally deferring or retrying a cycle upon a processor bus that is destined for a peripheral bus 有权
标题翻译：用于最佳延迟或重试一个周期的系统和方法，处理器总线上用于外设总线
公开(公告)号：US06216190B1
公开(公告)日：2001-04-10
申请号：US09164192
申请日：1998-09-30
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1342
CPC分类号： G06F13/4239
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the CPU bus for controlling the transfer of cycles from the CPU to the peripheral bus and memory bus. Those cycles can be arranged in order within the CPU bus pipeline. A subset of cycles destined for a peripheral bus can be stalled within a snoop phase associated with the CPU bus. Snoop stall can continue until a memory cycle is encountered upon the CPU bus pipeline within a phase prior to the snoop phase. Once the memory cycle progresses to the snoop phase, snoop stall can be discontinued and the previous, peripheral cycles can then be deferred and/or retried, allowing the memory cycle to be quickly dispatched through all phases of the CPU bus and onto the memory bus. In this fashion, memory cycles can be completed quickly, yet deferrals or retries are minimized to avoid the throughput penalty associated with deferring or retrying cycles back again through each phase of the CPU bus.
摘要翻译：提供一种具有耦合在CPU总线，外围总线和存储器总线之间的总线接口单元的计算机。总线接口单元包括连接到CPU总线的处理器控制器，用于控制从CPU到外围总线和存储器总线的周期传送。这些循环可以顺序排列在CPU总线管道中。在与CPU总线相关联的窥探阶段中，可能会停止发往外围总线的周期的子集。在窥探阶段之前的一个阶段，在CPU总线流水线上，Snoop停止可以继续，直到遇到内存循环。一旦存储器周期进行到窥探阶段，就可以停止侦听停止，然后可以延迟和/或重试先前的周边周期，从而允许通过CPU总线的所有阶段和存储器总线快速调度存储器周期。以这种方式，可以快速完成内存周期，但是延迟或重试最小化，以避免通过CPU总线的每个阶段再次延迟或重试周期相关的吞吐量损失。

6. 发明授权

US06209052B1 System and method for suppressing processor cycles to memory until after a peripheral device write cycle is acknowledged by the memory arbiter 有权
标题翻译：在存储器仲裁器确认外围设备写入周期之后，将处理器周期抑制到存储器的系统和方法
公开(公告)号：US06209052B1
公开(公告)日：2001-03-27
申请号：US09164194
申请日：1998-09-30
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1300
CPC分类号： G06F13/1605 , G06F13/4243
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues placed within address and data paths between the various controllers. The peripheral bus controller can decode a write cycle to memory, and the processor controller can thereafter request and be granted ownership of the CPU local bus. The address of the write cycle can then be snooped to determine if valid data exists within the CPU cache storage locations. If so, a writeback operation can occur. Ownership of the CPU bus is maintained by the bus interface unit during the snooping operation, as well as during writeback and the request of the memory bus by the peripheral-derived write cycle. It is not until ownership of the memory bus is granted by the memory arbiter that mastership is terminated by the bus interface unit. Accordingly, the bus interface unit keeps CPU-derived cycles off the CPU bus to ensure memory arbiter grants ownership to a write cycle from the peripheral bus. In this fashion, data from the peripheral bus can be stored in system memory before accessing that data by a CPU read cycle. The number of snoop cycles which the bus interface unit can initiate is determined by configuration registers programmed during power on, reset or boot up of computer.
摘要翻译：提供一种计算机，其具有耦合在CPU总线，外围总线（即PCI总线和/或图形总线）之间的总线接口单元和存储器总线。总线接口单元包括链接到相应总线的控制器，以及放置在各种控制器之间的地址和数据路径内的多个队列。外设总线控制器可以将写周期解码为存储器，然后处理器控制器可以请求并授予CPU本地总线的所有权。然后可以窥探写周期的地址，以确定CPU高速缓存存储位置中是否存在有效数据。如果是这样，可以进行回写操作。 CPU总线的所有权在侦听操作期间由总线接口单元维护，以及通过外设来源的写周期在写回和存储器总线的请求期间保持。直到存储器总线的所有权由总线接口单元终止主存的存储器仲裁器才被授予。因此，总线接口单元将CPU派生的周期从CPU总线保持，以确保存储器仲裁器将所有权授予来自外设总线的写周期。以这种方式，通过CPU读取周期访问该数据之前，来自外围总线的数据可以存储在系统存储器中。总线接口单元可以启动的窥探周期数由计算机上电，复位或启动时编程的配置寄存器决定。

7. 发明授权

US06202101B1 System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom 有权
标题翻译：同时请求输入/输出和存储器地址空间的系统和方法，同时保持从其发送和返回的数据的顺序
公开(公告)号：US06202101B1
公开(公告)日：2001-03-13
申请号：US09164189
申请日：1998-09-30
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1300
CPC分类号： G06F13/1621
摘要： A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred.
摘要翻译：提供了一种具有耦合在处理器总线，外围总线和存储器总线之间的总线接口单元的计算机。总线接口单元包括链接到处理器总线的处理器控制器，用于控制从处理器到外围总线和存储器总线的周期传送。这些周期最初作为请求转发，由此处理器控制器包括与外围设备请求队列分开的存储器请求队列。来自存储器和外围设备请求队列的请求可以同时排队到存储器和外围总线。这增强了读写请求的吞吐量; 但是，必须确保作为读请求返回的数据的正确排序和作为写请求结果传送的数据。在处理器控制器中还存在按顺序队列，该处理器控制器从周边和存储器请求队列记录请求被分派到外围设备和存储器总线的顺序。可以根据请求队列中的当前指针位置重新排序并将其显示给目的地。因此，按顺序队列跟踪数据在整个处理器总线上传输的顺序，与先前请求传送的顺序一致。

8. 发明授权

US06356972B1 System and method for concurrently requesting input/output and memory address space while maintaining order of data sent and returned therefrom 有权
标题翻译：同时请求输入/输出和存储器地址空间的系统和方法，同时保持从其发送和返回的数据的顺序
公开(公告)号：US06356972B1
公开(公告)日：2002-03-12
申请号：US09765773
申请日：2001-01-19
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F1314
CPC分类号： G06F13/1621
摘要： A computer is provided having a bus interface unit coupled between a processor bus, a peripheral bus, and a memory bus. The bus interface unit includes a processor controller linked to the processor bus for controlling the transfer of cycles from the processor to the peripheral bus and memory bus. Those cycles are initially forwarded as a request, whereby the processor controller includes a memory request queue separate from a peripheral request queue. Requests from the memory and peripheral request queues can be de-queued concurrently to the memory and peripheral buses. This enhances throughput of read and write requests; however, proper ordering of data returned as a result of read requests and data transferred as a result of write requests must be ensured. An in-order queue is also present in the processor controller which records the order in which the requests are dispatched to the peripheral and memory buses from the peripheral and memory request queues. Data ensuing from the request can be re-ordered and presented to the destination based on the current pointer position within the in-order queue. Thus, the in-order queue keeps track of the order in which data is transferred across the processor bus consistent with the order in which the previous requests were transferred.
摘要翻译：提供了一种具有耦合在处理器总线，外围总线和存储器总线之间的总线接口单元的计算机。总线接口单元包括链接到处理器总线的处理器控制器，用于控制从处理器到外围总线和存储器总线的周期传送。这些周期最初作为请求转发，由此处理器控制器包括与外围设备请求队列分开的存储器请求队列。来自存储器和外围设备请求队列的请求可以同时排队到存储器和外围总线。这增强了读写请求的吞吐量; 但是，必须确保作为读请求返回的数据的正确排序和作为写请求结果传送的数据。在处理器控制器中还存在按顺序队列，该处理器控制器从周边和存储器请求队列记录请求被分派到外围设备和存储器总线的顺序。可以根据请求队列中的当前指针位置重新排序并将其显示给目的地。因此，按顺序队列跟踪数据在整个处理器总线上传输的顺序，与先前请求传送的顺序一致。

9. 发明授权

US06199118B1 System and method for aligning an initial cache line of data read from an input/output device by a central processing unit 有权
标题翻译：用于对准由中央处理单元从输入/输出设备读取的初始高速缓存行数据的系统和方法
公开(公告)号：US06199118B1
公开(公告)日：2001-03-06
申请号：US09135703
申请日：1998-08-18
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F300
CPC分类号： G06F13/404 , G06F12/0879
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective busses and further includes a plurality of queues placed within address and data paths linking the various controllers. A processor controller coupled between a processor local bus determines if an address forwarded from the processor is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If the address (i.e., target address) is not the first address (initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. Quad words are received in sequential order and placed into the queue. When the quad words are sent to the CPU, they are in toggle order. This ensures the processor controller, and eventually the processor, will read quad words in toggle mode address order, even though the quad words are dispatched from the peripheral device in address-increasing (non-toggle mode) order.
摘要翻译：提供一种具有耦合在CPU总线，PCI总线和/或图形总线之间的总线接口单元的计算机。总线接口单元包括链接到相应总线的控制器，还包括放置在连接各种控制器的地址和数据路径内的多个队列。耦合在处理器本地总线之间的处理器控制器确定从处理器转发的地址是否是用于选择构成高速缓存行的四字组的地址序列中的第一地址。如果地址（即，目标地址）不是该序列中的第一个地址（初始地址），则修改目标地址，使其成为该序列中的初始地址。四个字按顺序接收并放入队列。当四位字被发送到CPU时，它们处于切换顺序。这确保处理器控制器，最终处理器将以切换模式地址顺序读取四个字，即使以寻址增加（非切换模式）顺序从外围设备发送四个字。

10. 发明授权

US06160562A System and method for aligning an initial cache line of data read from local memory by an input/output device 有权
标题翻译：用于通过输入/输出设备对准从本地存储器读取的数据的初始高速缓存行的系统和方法
公开(公告)号：US06160562A
公开(公告)日：2000-12-12
申请号：US135620
申请日：1998-08-18
申请人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
发明人： Kenneth T. Chin , Clarence K. Coffee , Michael J. Collins , Jerome J. Johnson , Phillip M. Jones , Robert A. Lester , Gary J. Piccirillo
IPC分类号： G06F12/08 , G06F13/40 , G06F13/14
CPC分类号： G06F12/0879 , G06F13/404
摘要： A computer is provided having a bus interface unit coupled between a CPU bus, a PCI bus and/or a graphics bus. The bus interface unit includes controllers linked to the respective buses and further includes a plurality of queues placed within address and data paths linking the various controllers. An interface controller coupled between a peripheral bus (excluding the CPU local bus) determines if an address forwarded from a peripheral device is the first address within a sequence of addresses used to select a set of quad words constituting a cache line. If that address (i.e., target address) is not the first address (i.e., initial address) in that sequence, then the target address is modified so that it becomes the initial address in that sequence. An offset between the target address and the modified address is denoted as a count value. The initial address aligns the reads to a cacheline boundary and stores in successive order the quad words of the cacheline in the queue of the bus interface unit. Quad words arriving in the queue prior to a quad word attributed to the target address are discarded. This ensures the interface controller, and eventually the peripheral device, will read quad words in successive address order, and all subsequently read quad words will also be sent in successive order until the peripheral read transaction is complete.
摘要翻译：提供一种具有耦合在CPU总线，PCI总线和/或图形总线之间的总线接口单元的计算机。总线接口单元包括链接到各个总线的控制器，还包括放置在连接各种控制器的地址和数据路径内的多个队列。耦合在外围总线（不包括CPU本地总线）之间的接口控制器确定从外围设备转发的地址是否是用于选择构成高速缓存行的一组四字的地址序列内的第一地址。如果该地址（即，目标地址）不是该序列中的第一地址（即，初始地址），则修改目标地址，使其成为该序列中的初始地址。目标地址与修改地址之间的偏移量表示为计数值。初始地址将读取对齐到高速缓存行边界，并以连续顺序存储总线接口单元队列中的高速缓存行的四个字。在归因于目标地址的四字之前到达队列的四字被丢弃。这确保接口控制器以及最终的外围设备将以连续的地址顺序读取四个字，并且所有随后读取的四字都将以连续的顺序发送，直到外设读取事务完成。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式