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1. 发明授权

US07739637B2 Partial good schema for integrated circuits having parallel execution units 失效
标题翻译：具有并行执行单元的集成电路的部分良好架构
公开(公告)号：US07739637B2
公开(公告)日：2010-06-15
申请号：US12362541
申请日：2009-01-30
申请人： Kenneth Joseph Goodnow , Michael Richard Ouellette , Stephen Gerard Shuma , Peter Albert Twombly
发明人： Kenneth Joseph Goodnow , Michael Richard Ouellette , Stephen Gerard Shuma , Peter Albert Twombly
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Processing engines (PE's) disposed on the substrate. Each processing engine includes a measurement and storage unit, and a PE controller coupled to each of the processing engines. The processing engines perform self-tests and store the results of the self-tests in the measurement and storage unit. The PE controller reads the results and selects a sub-set of processing engines based on the results and an optimization algorithm.
摘要翻译：处理引擎（PE）设置在基板上。每个处理引擎包括测量和存储单元以及耦合到每个处理引擎的PE控制器。处理引擎执行自检并将测试结果存储在测量和存储单元中。 PE控制器根据结果和优化算法读取结果并选择一组处理引擎。

2. 发明申请

US20090256591A1 STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于系统的结构和在集成电路上管理一组可编程熔丝的方法
公开(公告)号：US20090256591A1
公开(公告)日：2009-10-15
申请号：US12103519
申请日：2008-04-15
申请人： John Atkinson Fifield , Michael Richard Ouellette
发明人： John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H03K19/173
CPC分类号： H03K19/1733
摘要： Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
摘要翻译：公开了一种用于在集成电路上管理一组可编程熔丝的系统和方法的设计结构。

3. 发明授权

US06229754B1 Write through function for a memory 有权
标题翻译：写入内存的功能
公开(公告)号：US06229754B1
公开(公告)日：2001-05-08
申请号：US09501393
申请日：2000-02-09
申请人： Eric Lee Carter , Moon Ho Lee , Michael Richard Ouellette , Geoffrey Wang , Michael Hemsley Wood
发明人： Eric Lee Carter , Moon Ho Lee , Michael Richard Ouellette , Geoffrey Wang , Michael Hemsley Wood
IPC分类号： G11C800
CPC分类号： G11C8/16
摘要： A multi-port electronic memory has a write through capability. Control features for enabling a write through path to an output and subsequently disabling without causing data errors due to design and technology variations are provided. Control features are especially beneficial for use with compilable SRAM books.
摘要翻译：多端口电子存储器具有写入功能。提供了用于启用到输出的写入路径并随后禁用而不会由于设计和技术变化而导致数据错误的控制特征。控制功能特别适用于可编译SRAM书籍。

4. 发明授权

US07688654B2 Structure for differential eFUSE sensing without reference fuses 有权
标题翻译：不带参考保险丝的差分eFUSE检测结构
公开(公告)号：US07688654B2
公开(公告)日：2010-03-30
申请号：US11769925
申请日：2007-06-28
申请人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
发明人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： G11C11/063
CPC分类号： G11C17/16 , G11C17/18
摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和耦合到参考电压的第二节点。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

5. 发明授权

US07139944B2 Method and system for determining minimum post production test time required on an integrated circuit device to achieve optimum reliability 有权
标题翻译：用于确定集成电路设备实现最佳可靠性所需的最小后期制作测试时间的方法和系统
公开(公告)号：US07139944B2
公开(公告)日：2006-11-21
申请号：US10604887
申请日：2003-08-25
申请人： Tange Nan Barbour , Thomas S. Barnett , Matthew Sean Grady , William Vincent Huott , Michael Richard Ouellette
发明人： Tange Nan Barbour , Thomas S. Barnett , Matthew Sean Grady , William Vincent Huott , Michael Richard Ouellette
IPC分类号： G11C29/00 , G06F11/00
CPC分类号： G11C29/44 , G11C29/56008 , G11C2029/1208 , G11C2029/4402
摘要： A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.
摘要翻译：一种用于在集成电路器件上确定最小后期制作测试时间以实现利用缺陷计数的该器件的最佳可靠性的方法和系统。对集成电路装置上的缺陷单元或缺陷单元（DEFECTS）的有缺陷单元的数量进行计数，该计数作为确定最小测试时间的基础。更高数量的缺陷导致更长的后期测试，以实现集成电路器件的最佳可靠性。 DEFECTS的数量可以在集成电路设备内部的设备上进行计数，并可用于确定最低要求的测试时间。还可以通过拦截路由到另一设备的信息，在集成电路设备外部获得缺陷数量。内部和外部提供的信息还可以显示缺陷的物理位置，以进一步完善最低要求的测试时间。

6. 发明授权

US5918003A Enhanced built-in self-test circuit and method 失效
标题翻译：增强内置自检电路及方法
公开(公告)号：US5918003A
公开(公告)日：1999-06-29
申请号：US800345
申请日：1997-02-14
申请人： Garrett Stephen Koch , Michael Richard Ouellette , Reid Allen Wistort
发明人： Garrett Stephen Koch , Michael Richard Ouellette , Reid Allen Wistort
IPC分类号： G01R31/3185 , G06F11/00
CPC分类号： G01R31/318555
摘要： An Array Built-In Self Test (ABIST) circuit places on-chip circuits such as memory arrays in a known state, then stops. In the alternative, the ABIST circuit may initialize to a particular subcycle within a pattern sequence, and repeatedly loop on the subcycle, or repeatedly loop on the entire pattern sequence.
摘要翻译：阵列内置自检（ABIST）电路将片上电路（如存储器阵列）置于已知状态，然后停止。在替代方案中，ABIST电路可以初始化到模式序列内的特定子周期，并且在子周期上重复循环，或者在整个模式序列上重复循环。

7. 发明授权

US08595557B2 Method and apparatus for verifying memory testing software 有权
标题翻译：用于验证存储器测试软件的方法和装置
公开(公告)号：US08595557B2
公开(公告)日：2013-11-26
申请号：US10906508
申请日：2005-02-23
申请人： Eric Jasinski , Michael Richard Ouellette , Jeremy Paul Rowland
发明人： Eric Jasinski , Michael Richard Ouellette , Jeremy Paul Rowland
IPC分类号： G06F11/00
CPC分类号： G11C29/12 , G11C29/56 , G11C2029/0405 , G11C2029/5604
摘要： A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
摘要翻译：公开了一种用于验证存储器测试软件的精度的方法。内存自检（BIST）故障控制功能用于在存储器件的存储器阵列内的各个预定位置处产生多个模拟存储器故障。然后，存储器阵列由存储器测试器测试。之后，由存储器测试仪指示的所有存储器故障由逻辑到物理映射软件产生一个故障映射。位故障映射提供由逻辑到物理映射软件导出的所有故障存储器位置。然后将由逻辑到物理映射软件导出的故障存储器位置与预定的存储器位置进行比较，以验证逻辑到物理映射软件的准确性。

8. 发明授权

US07541834B1 System and the methods of managing a set of programmable fuses on an integrated circuit 失效
标题翻译：系统和在集成电路上管理一组可编程保险丝的方法
公开(公告)号：US07541834B1
公开(公告)日：2009-06-02
申请号：US12121373
申请日：2008-05-15
申请人： John Atkinson Fifield , Michael Richard Ouellette
发明人： John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H03K19/173 , H01H37/76
CPC分类号： H03K19/1736 , G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
摘要翻译：公开了一种用于在集成电路上管理一组可编程熔丝的系统和方法的设计结构。

9. 发明申请

US20080052542A1 System and Method to Optimize Multi-Core Microprocessor Performance Using Voltage Offsets 失效
标题翻译：使用电压偏移优化多核微处理器性能的系统和方法
公开(公告)号：US20080052542A1
公开(公告)日：2008-02-28
申请号：US11466891
申请日：2006-08-24
申请人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
发明人： Louis Bennie Capps , Warren D. Dyckman , Joanne Ferris , Anand Haridass , James Douglas Jordan , Ronald Edward Newhart , Michael Richard Ouellette , Michael Jay Shapiro
IPC分类号： G06F1/00
CPC分类号： G06F1/26
摘要： A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.
摘要翻译：提出了使用电压偏移来优化多核微处理器性能的系统和方法。多核设备测试每个处理器内核，以便识别每个处理器内核的最佳电源电压。反过来，该设备基于每个处理器核心的所识别的最佳电源电压来配置每个处理器核心的电压偏移网络。结果，从多核设备的主电压中减去由电压偏移网络产生的偏移电压，这导致电压偏移网络向每个处理器核提供最佳电源电压。电压偏移网络可以包括熔丝以产生固定的电压偏移，或者电压偏移网络可以包括在多核装置的操作期间动态地调节电压偏移的控制电路。

10. 发明申请

US20080001251A1 STRUCTURE FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：不参考熔丝的不同EFEX感应结构
公开(公告)号：US20080001251A1
公开(公告)日：2008-01-03
申请号：US11769925
申请日：2007-06-28
申请人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
发明人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和耦合到参考电压的第二节点。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

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