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1. 发明授权

US07688654B2 Structure for differential eFUSE sensing without reference fuses 有权
标题翻译：不带参考保险丝的差分eFUSE检测结构
公开(公告)号：US07688654B2
公开(公告)日：2010-03-30
申请号：US11769925
申请日：2007-06-28
申请人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
发明人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： G11C11/063
CPC分类号： G11C17/16 , G11C17/18
摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和耦合到参考电压的第二节点。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

2. 发明申请

US20080001251A1 STRUCTURE FOR DIFFERENTIAL EFUSE SENSING WITHOUT REFERENCE FUSES 有权
标题翻译：不参考熔丝的不同EFEX感应结构
公开(公告)号：US20080001251A1
公开(公告)日：2008-01-03
申请号：US11769925
申请日：2007-06-28
申请人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
发明人： Darren Lane Anand , John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H01L29/00
CPC分类号： G11C17/16 , G11C17/18
摘要： A design structure comprising a differential fuse sensing system, which includes a fuse leg configured for introducing a sense current through an electrically programmable fuse (eFUSE) to be sensed, and a differential sense amplifier having a first input node coupled to the fuse leg and a second node coupled to a reference voltage. The fuse leg further includes a current supply device controlled by a variable reference current generator configured to generate an output signal therefrom such that the voltage on the first input node of the sense amplifier is equal to the voltage on the second input node of the sense amplifier whenever the resistance value of the eFUSE is equal to the resistance value of a programmable variable resistance device included within the variable reference current generator.
摘要翻译：一种设计结构，包括差分熔丝感测系统，其包括被配置用于通过要被感测的电可编程熔丝（eFUSE）引入感测电流的熔丝腿，以及具有耦合到保险丝腿的第一输入节点的差分读出放大器和耦合到参考电压的第二节点。保险丝腿还包括由可变参考电流发生器控制的电流供应装置，其被配置为从其产生输出信号，使得读出放大器的第一输入节点上的电压等于读出放大器的第二输入节点上的电压每当eFUSE的电阻值等于包括在可变参考电流发生器内的可编程可变电阻器件的电阻值时。

3. 发明申请

US20090256591A1 STRUCTURE FOR SYSTEMS AND METHODS OF MANAGING A SET OF PROGRAMMABLE FUSES ON AN INTEGRATED CIRCUIT 审中-公开
标题翻译：用于系统的结构和在集成电路上管理一组可编程熔丝的方法
公开(公告)号：US20090256591A1
公开(公告)日：2009-10-15
申请号：US12103519
申请日：2008-04-15
申请人： John Atkinson Fifield , Michael Richard Ouellette
发明人： John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H03K19/173
CPC分类号： H03K19/1733
摘要： Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
摘要翻译：公开了一种用于在集成电路上管理一组可编程熔丝的系统和方法的设计结构。

4. 发明授权

US07541834B1 System and the methods of managing a set of programmable fuses on an integrated circuit 失效
标题翻译：系统和在集成电路上管理一组可编程保险丝的方法
公开(公告)号：US07541834B1
公开(公告)日：2009-06-02
申请号：US12121373
申请日：2008-05-15
申请人： John Atkinson Fifield , Michael Richard Ouellette
发明人： John Atkinson Fifield , Michael Richard Ouellette
IPC分类号： H03K19/173 , H01H37/76
CPC分类号： H03K19/1736 , G11C17/18 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a design structure for systems and methods of managing a set of programmable fuses on an integrated circuit.
摘要翻译：公开了一种用于在集成电路上管理一组可编程熔丝的系统和方法的设计结构。

5. 发明授权

US06577156B2 Method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox 有权
公开(公告)号：US06577156B2
公开(公告)日：2003-06-10
申请号：US09731147
申请日：2000-12-05
申请人： Darren L. Anand , John Edward Barth, Jr. , John Atkinson Fifield , Pamela Sue Gillis , Peter O. Jakobsen , Douglas Wayne Kemerer , David E. Lackey , Steven Frederick Oakland , Michael Richard Ouellette , William Robert Tonti
发明人： Darren L. Anand , John Edward Barth, Jr. , John Atkinson Fifield , Pamela Sue Gillis , Peter O. Jakobsen , Douglas Wayne Kemerer , David E. Lackey , Steven Frederick Oakland , Michael Richard Ouellette , William Robert Tonti
IPC分类号： G11C700
CPC分类号： G11C29/80 , G11C29/802
摘要： A method and apparatus for initializing an integrated circuit using compressed data from a remote fusebox allows a reduction in the number of fuses required to repair or customize an integrated circuit and allows fuses to be grouped outside of the macros repaired by the fuses. The remote location of fuses allows flexibility in the placement of macros having redundant repair capability, as well as a preferable grouping of fuses for both programming convenience and circuit layout facilitation. The fuses are arranged in rows and columns and represent control words and run-length compressed data to provide a greater quantity of repair points per fuse. The data can be loaded serially into shift registers and shifted to the macro locations to control the selection of redundant circuits to repair integrated circuits having defects or to customize logic.

6. 发明授权

US5682394A Fault tolerant computer memory systems and components employing dual level error correction and detection with disablement feature 失效
标题翻译：容错计算机存储器系统和采用双级错误校正和检测功能的组件
公开(公告)号：US5682394A
公开(公告)日：1997-10-28
申请号：US012186
申请日：1993-02-02
申请人： Robert Martin Blake , Douglas Craig Bossen , Chin-Long Chen , John Atkinson Fifield , Howard Leo Kalter
发明人： Robert Martin Blake , Douglas Craig Bossen , Chin-Long Chen , John Atkinson Fifield , Howard Leo Kalter
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/1052 , G06F11/1008
摘要： In a memory system comprising a plurality of memory units each of which possesses unit-level error correction capabilities and each of which is tied to a system level error correction function, memory reliability is enhanced by providing a mechanism for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
摘要翻译：在包括多个存储器单元的存储器系统中，每个存储器单元具有单位级错误校正能力，并且每个都与系统级错误校正功能相关联，通过提供用于禁用单元级错误校正的机制来增强存储器的可靠性能力，例如，响应于在一个存储器单元中发生不可校正的错误。这种禁用纠错功能的反直觉方法仍然提高了整体存储系统的可靠性，因为它可以使用补充/重新补充算法，这取决于是否存在可重复的错误以进行正确的操作。因此，在高封装密度下越来越需要的芯片级误差校正系统采用不干扰系统级误差校正方法的方式。

7. 发明授权

US06975169B2 Low-voltage differential amplifier 失效
标题翻译：低压差分放大器
公开(公告)号：US06975169B2
公开(公告)日：2005-12-13
申请号：US10707891
申请日：2004-01-21
申请人： John Atkinson Fifield , Steven Harley Lamphier
发明人： John Atkinson Fifield , Steven Harley Lamphier
IPC分类号： H03F3/45
CPC分类号： H03F3/4521 , H03F3/45183 , H03F2200/513 , H03F2203/45366
摘要： A low-voltage differential amplifier circuit is disclosed. The low-voltage differential amplifier circuit includes a first differential amplifier, a second differential amplifier and a summing circuit. The first differential amplifier receives a pair of differential input signals to generate a first output. The second differential amplifier receives the same pair of differential input signals to generate a second output. The summing circuit sums the first output of the first differential amplifier and the second output of the second differential amplifier to provide a common output.
摘要翻译：公开了一种低压差分放大器电路。低压差分放大电路包括第一差分放大器，第二差分放大器和求和电路。第一差分放大器接收一对差分输入信号以产生第一输出。第二差分放大器接收同一对差分输入信号以产生第二输出。求和电路将第一差分放大器的第一输出和第二差分放大器的第二输出相加以提供公共输出。

8. 发明授权

US5796270A Self-timed driver circuit 失效
公开(公告)号：US5796270A
公开(公告)日：1998-08-18
申请号：US703172
申请日：1996-08-22
申请人： John Atkinson Fifield , Glenn Peter Giacalone , Peter Joel Jenkins
发明人： John Atkinson Fifield , Glenn Peter Giacalone , Peter Joel Jenkins
IPC分类号： H03K19/017 , H03K19/0185 , H03K19/0175
CPC分类号： H03K19/01721 , H03K19/018521
摘要： A driver circuit provides for selectively changing the state of an output signal, such as a pre-charged dynamic bus signal. The circuit detects whether or not the data is the opposite state as the pre-charged bus signal, and if so, it drives the bus to the appropriate state. The output from the circuit is self-timed when data can be driven onto the bus as soon as data is valid, i.e., data propagates from the input of the circuit to the bus without depending on a clock or other timing edge.

9. 发明授权

US06737907B2 Programmable DC voltage generator system 失效
标题翻译：可编程直流电压发生器系统
公开(公告)号：US06737907B2
公开(公告)日：2004-05-18
申请号：US09898328
申请日：2001-07-03
申请人： Louis L. Hsu , Li-Kong Wang , John Atkinson Fifield , Wayne F. Ellis
发明人： Louis L. Hsu , Li-Kong Wang , John Atkinson Fifield , Wayne F. Ellis
IPC分类号： G05F110
CPC分类号： H02M3/073 , H02M2001/0012 , H02M2001/0025
摘要： A digitally programmable DC voltage generator system having a programming circuit for controlling a control circuit of a voltage generator system. The programming circuit receives an input control signal, processes the input control signal, and generates an output control signal to the control circuit of the voltage generator system for controlling the control circuit in accordance with the input control signal. The control circuit includes a limiter circuit and an oscillator circuit. The output control signal controls at least one of the limiter circuit for disabling the oscillator circuit upon reaching a target output voltage, and the oscillator circuit for controlling the pumping speed of the oscillator circuit.
摘要翻译：一种具有用于控制电压发生器系统的控制电路的编程电路的数字可编程直流电压发生器系统。编程电路接收输入控制信号，处理输入控制信号，并将输出控制信号产生到电压发生器系统的控制电路，用于根据输入控制信号控制控制电路。控制电路包括限幅电路和振荡电路。输出控制信号控制至少一个限制电路，用于在达到目标输出电压时使振荡器电路无效，以及用于控制振荡器电路的泵送速度的振荡器电路。

10. 发明授权

US06531410B2 Intrinsic dual gate oxide MOSFET using a damascene gate process 有权
公开(公告)号：US06531410B2
公开(公告)日：2003-03-11
申请号：US09795610
申请日：2001-02-27
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L2131
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.

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