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1. 发明授权

US08595557B2 Method and apparatus for verifying memory testing software 有权
标题翻译：用于验证存储器测试软件的方法和装置
公开(公告)号：US08595557B2
公开(公告)日：2013-11-26
申请号：US10906508
申请日：2005-02-23
申请人： Eric Jasinski , Michael Richard Ouellette , Jeremy Paul Rowland
发明人： Eric Jasinski , Michael Richard Ouellette , Jeremy Paul Rowland
IPC分类号： G06F11/00
CPC分类号： G11C29/12 , G11C29/56 , G11C2029/0405 , G11C2029/5604
摘要： A method for verifying the accuracy of memory testing software is disclosed. A built-in self test (BIST) fail control function is utilized to generate multiple simulated memory fails at various predetermined locations within a memory array of a memory device. The memory array is then tested by a memory tester. Afterwards, a bit fail map is generated by the logical-to-physical mapping software based on all the memory fails indicated by the memory tester. The bit fail map provides all the fail memory locations derived by the logical-to-physical mapping software. The fail memory locations derived by the logical-to-physical mapping software are then compared to the predetermined memory locations to verify the accuracy of the logical-to-physical mapping software.
摘要翻译：公开了一种用于验证存储器测试软件的精度的方法。内存自检（BIST）故障控制功能用于在存储器件的存储器阵列内的各个预定位置处产生多个模拟存储器故障。然后，存储器阵列由存储器测试器测试。之后，由存储器测试仪指示的所有存储器故障由逻辑到物理映射软件产生一个故障映射。位故障映射提供由逻辑到物理映射软件导出的所有故障存储器位置。然后将由逻辑到物理映射软件导出的故障存储器位置与预定的存储器位置进行比较，以验证逻辑到物理映射软件的准确性。

2. 发明授权

US06496432B2 Method and apparatus for testing a write function of a dual-port static memory cell 有权
公开(公告)号：US06496432B2
公开(公告)日：2002-12-17
申请号：US09733295
申请日：2000-12-08
申请人： Michael Richard Ouellette , Jeremy Paul Rowland , David Jerome Wager
发明人： Michael Richard Ouellette , Jeremy Paul Rowland , David Jerome Wager
IPC分类号： G11C2900
CPC分类号： G11C8/16 , G11C29/02
摘要： A method and apparatus for testing a write function of a dual-port static memory cell during a concurrent read/write cycle on a memory cell is disclosed. A memory cell of a dual-port static memory is read via a first port of the memory cell. After the read operation, the standard bitline restore operation that normally occurs after a read or write operation is suppressed from occurring on the bitlines for the first port. Then, the memory cell is read again via the first port at the same time the memory cell is being written via a second port with a logical data value that is opposite to the logical data value being read from the first port. After the completion of the write operation, the bitlines for the first and second ports are restored by a bitline restore operation. Finally, the logical data value in the memory cell is verified for its correctness.

3. 发明授权

US06442085B1 Self-Test pattern to detect stuck open faults 失效
标题翻译：自检模式，用于检测卡住的打开故障
公开(公告)号：US06442085B1
公开(公告)日：2002-08-27
申请号：US09677681
申请日：2000-10-02
申请人： Michael Thomas Fragano , Jeffery Howard Oppold , Michael Richard Ouellette , Jeremy Paul Rowland
发明人： Michael Thomas Fragano , Jeffery Howard Oppold , Michael Richard Ouellette , Jeremy Paul Rowland
IPC分类号： G11C700
CPC分类号： G11C29/02
摘要： A testing method and device for detecting the existence of “stuck-open”, faults within static decoder circuits of a SRAM. The device and method make use of a novel pattern that fully tests static decoders used with an SRAM integrated circuit. The test pattern is selected so as to cause a transition on each parallel FET in a decoder circuit. The test pattern simulates multiple random accesses to the SRAM by modifying the traditional sequential, unique address pattern. The invention uses a two-dimensional pattern in that it separately tests rows and column decoders. In the first part of the test the input address to the column decoders is held constant while the row decoders are cycled through two sets of N iterations where N is the number of row address bits to be decoded. During the second part of the test the input address to the row decoders is held constant while the column decoders are cycled through two sets of M iterations where M is the number of column address bits to be decoded.
摘要翻译：一种用于检测SRAM的静态解码器电路中存在“卡住开路”故障的测试方法和装置。该器件和方法利用了一种全新的模式来完全测试SRAM集成电路中使用的静态解码器。选择测试图案以便在解码器电路中的每个并联FET上产生转换。测试模式通过修改传统的顺序唯一地址模式来模拟对SRAM的多次随机访问。本发明使用二维图案，它分别测试行和列解码器。在测试的第一部分中，列解码器的输入地址保持不变，而行解码器循环通过两组N次迭代，其中N是要解码的行地址位数。在测试的第二部分期间，行解码器的输入地址保持不变，而列解码器循环通过两组M次迭代，其中M是待解码的列地址位数。

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