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    • 1. 发明申请
      US20090122619A1 Enhanced DRAM with Embedded Registers 审中-公开
    • Enhanced DRAM with Embedded Registers
    • 具有嵌入式寄存器的增强型DRAM
    • US20090122619A1
    • 2009-05-14
    • US12116097
    • 2008-05-06
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
    • G11C7/00 , G11C8/00
    • G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
    • An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
    • 增强型DRAM包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 2. 发明授权
      US5699317A Enhanced DRAM with all reads from on-chip cache and all writers to memory array 失效
    • Enhanced DRAM with all reads from on-chip cache and all writers to memory array
    • 增强型DRAM，具有从片上缓存和所有写入器到存储器阵列的所有读取
    • US5699317A
    • 1997-12-16
    • US319289
    • 1994-10-06
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
    • Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
    • G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G11C11/409
    • G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
    • An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
    • 增强型动态随机存取存储器（DRAM）包含锁存器形式的嵌入式行寄存器。 行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。 当用作片上缓存时，这些寄存器保存频繁访问的数据。 该数据对应于在特定地址处存储在DRAM中的数据。 当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。 如果地址相同，则以静态随机存取存储器（SRAM）速度读取高速缓存数据。 DRAM与此读取分离。 在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。 刷新或预充电与缓存读取同时发生。 如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5327026A Self-timed bootstrap decoder 失效
    • Self-timed bootstrap decoder
    • 自定义自举解码器
    • US5327026A
    • 1994-07-05
    • US18802
    • 1993-02-17
    • Kim C. Hardee , Kenneth J. Mobley
    • Kim C. Hardee , Kenneth J. Mobley
    • G11C11/407 , G11C8/10 , H03K17/10
    • G11C8/10
    • A row decoder that includes circuitry to provide a self-timed bootstrap signal. The self-timed bootstrap signal is generated in response to the selection of the row decoder. At the same time, a capacitive device is charged in order to bootstrap a word line. The self-timed bootstrap signal causes a clock generator circuit to output a clock signal that will be used to bootstrap the word line. The self-timed bootstrap signal may be generated by other row decoders. The generation of the self-timed bootstrap signal by a row decoder is responsive to any variations in that decoder, thus always providing an accurate and precise timing of the clock signal to be used for the bootstrapping.
    • 行解码器，其包括提供自定时自举信号的电路。 响应于行解码器的选择而产生自定时自举信号。 同时，为了引导字线，电容器件被充电。 自定时自举信号使时钟发生器电路输出将用于引导字线的时钟信号。 自定时自举信号可以由其他行解码器产生。 由行解码器产生自定时自举信号响应于该解码器中的任何变化，因此总是提供用于自举的时钟信号的准确和精确的定时。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 8. 发明授权
      US5991851A Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control 失效
    • Enhanced signal processing random access memory device utilizing a DRAM memory array integrated with an associated SRAM cache and internal refresh control
    • 利用与相关联的SRAM缓存和内部刷新控制集成的DRAM存储器阵列的增强型信号处理随机存取存储器件
    • US5991851A
    • 1999-11-23
    • US850802
    • 1997-05-02
    • Michael Alwais , Kenneth J. Mobley
    • Michael Alwais , Kenneth J. Mobley
    • G11C11/41 , G11C11/401 , G11C11/406 , G06F12/00
    • G11C11/406
    • An enhanced digital signal processing random access memory device utilizing a highly density DRAM core memory array integrated with an SRAM cache and internal refresh control functionality which may be provided in an integrated circuit package which is pin-compatible with industry standard SRAM memory devices. The memory device provides a high speed memory access device of particular utility in conjunction with DSP processors with performance equivalent to that of SRAM memory devices but requiring a significantly small die size which allows for the provision of greater effective memory capacity per die area. The internal refresh functionality of the device provides for all refresh operations to the DRAM memory array to occur transparently to the device user and provides control signals alerting the associated controller when refresh operations are being performed.
    • 利用与SRAM缓存集成的高密度DRAM内存存储器阵列和内部刷新控制功能的增强型数字信号处理随机存取存储器件，其可以在与工业标准SRAM存储器器件引脚兼容的集成电路封装中提供。 存储器件提供了具有与SRAM存储器件相当性能的DSP处理器特别实用的高速存储器访问设备，但是需要显着小的管芯尺寸，这允许每个管芯区域提供更大的有效存储器容量。 该设备的内部刷新功能提供了DRAM存储器阵列的所有刷新操作，以便对设备用户透明地发生，并且提供在执行刷新操作时提示相关控制器的控制信号。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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