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1. 发明申请

US20090122619A1 Enhanced DRAM with Embedded Registers 审中-公开
标题翻译：具有嵌入式寄存器的增强型DRAM
公开(公告)号：US20090122619A1
公开(公告)日：2009-05-14
申请号：US12116097
申请日：2008-05-06
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, JR.
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

2. 发明授权

US5699317A Enhanced DRAM with all reads from on-chip cache and all writers to memory array 失效
标题翻译：增强型DRAM，具有从片上缓存和所有写入器到存储器阵列的所有读取
公开(公告)号：US5699317A
公开(公告)日：1997-12-16
申请号：US319289
申请日：1994-10-06
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G11C11/409
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
摘要： An enhanced dynamic random access memory (DRAM) contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at static random access memory (SRAM) speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型动态随机存取存储器（DRAM）包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以静态随机存取存储器（SRAM）速度读取高速缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

3. 发明授权

US07370140B2 Enhanced DRAM with embedded registers 失效
标题翻译：具有嵌入式寄存器的增强型DRAM
公开(公告)号：US07370140B2
公开(公告)日：2008-05-06
申请号：US09962287
申请日：2001-09-24
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
IPC分类号： G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

4. 发明授权

US5721862A Enhanced DRAM with single row SRAM cache for all device read operations 失效
标题翻译：具有单行SRAM缓存的增强型DRAM，用于所有器件读取操作
公开(公告)号：US5721862A
公开(公告)日：1998-02-24
申请号：US460665
申请日：1995-06-02
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones, Jr.
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register. Additionally, the row registers/memory cache is sized to contain a row of data of the DRAM array. Furthermore, a single column decoder addresses corresponding locations in both the memory cache and the DRAM array. And finally, all reads are only from the memory cache.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。另外，行寄存器/存储器高速缓冲存储器的大小可以包含DRAM阵列的一行数据。此外，单列解码器解决存储器高速缓存和DRAM阵列中的相应位置。最后，所有的读取只能从内存缓存中读取。

5. 发明授权

US06347357B1 Enhanced DRAM with embedded registers 失效
标题翻译：具有嵌入式寄存器的增强型DRAM
公开(公告)号：US06347357B1
公开(公告)日：2002-02-12
申请号：US09182994
申请日：1998-10-30
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
IPC分类号： G06F1200
CPC分类号： G11C7/106 , G06F12/0893 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , G11C11/005 , G11C11/406 , G11C11/4096 , Y02D10/13
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.
摘要翻译：增强型DRAM包含锁存器形式的嵌入式行寄存器。行寄存器与DRAM阵列相邻，并且当DRAM包括一组子阵列时，行寄存器位于DRAM子阵列之间。当用作片上缓存时，这些寄存器保存频繁访问的数据。该数据对应于在特定地址处存储在DRAM中的数据。当将地址提供给DRAM时，将其与存储在高速缓存中的数据的地址进行比较。如果地址相同，则以SRAM速度读取缓存数据。 DRAM与此读取分离。在该高速缓存读取期间，DRAM还保持空闲，除非系统选择预充电或刷新DRAM。刷新或预充电与缓存读取同时发生。如果地址不一样，则DRAM被访问，并且嵌入式寄存器被重新加载在该新DRAM地址处的数据。 DRAM的异步操作是通过将DRAM寄存器与DRAM阵列去耦合来实现的，从而允许DRAM单元在行寄存器的读取期间被预充电或刷新。

6. 发明授权

US5887272A Enhanced DRAM with embedded registers 失效
公开(公告)号：US5887272A
公开(公告)日：1999-03-23
申请号：US888371
申请日：1997-07-03
申请人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
发明人： Ronald H. Sartore , Kenneth J. Mobley , Donald G. Carrigan , Oscar Frederick Jones
IPC分类号： G06F12/08 , G11C7/10 , G11C11/00 , G11C11/401 , G11C11/406 , G11C11/4096 , G11C11/41 , G06F12/00
CPC分类号： G11C7/106 , G06F12/0893 , G11C11/005 , G11C11/406 , G11C11/4096 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1087 , Y02B60/1225
摘要： An enhanced DRAM contains embedded row registers in the form of latches. The row registers are adjacent to the DRAM array, and when the DRAM comprises a group of subarrays, the row registers are located between DRAM subarrays. When used as on-chip cache, these registers hold frequently accessed data. This data corresponds to data stored in the DRAM at a particular address. When an address is supplied to the DRAM, it is compared to the address of the data stored in the cache. If the addresses are the same, then the cache data is read at SRAM speeds. The DRAM is decoupled from this read. The DRAM also remains idle during this cache read unless the system opts to precharge or refresh the DRAM. Refresh or precharge occur concurrently with the cache read. If the addresses are not the same, then the DRAM is accessed and the embedded register is reloaded with the data at that new DRAM address. Asynchronous operation of the DRAM is achieved by decoupling the row registers from the DRAM array, thus allowing the DRAM cells to be precharged or refreshed during a read of the row register.

7. 发明授权

US06263398B1 Integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache 失效
标题翻译：包含非易失性存储器阵列和相对较快的存取时间存储器高速缓存的集成电路存储器件
公开(公告)号：US06263398B1
公开(公告)日：2001-07-17
申请号：US09021132
申请日：1998-02-10
申请人： Craig Taylor , Donald G. Carrigan , Mike Alwais
发明人： Craig Taylor , Donald G. Carrigan , Mike Alwais
IPC分类号： G06F1200
CPC分类号： G06F12/0893 , G06F2212/2022 , G06F2212/3042 , G11C11/005 , G11C16/26
摘要： An integrated circuit memory device incorporating a non-volatile memory array and a relatively faster access time memory cache integrated monolithically therewith improves the overall access time in page and provides faster cycle time for read operations. In a particular embodiment, the cache may be provided as static random access memory (“SRAM”) and the non-volatile memory array provided as ferroelectric random access memory wherein on a read, the row is cached and the write back cycle is started allowing subsequent in page reads to occur very quickly. If in page accesses are sufficient the memory array precharge may be hidden and writes can occur utilizing write back or write through caching. In alternative embodiments, the non-volatile memory array may comprise electrically erasable read only memory (“EEPROM”) or Flash memory in conjunction with an SRAM cache or a ferroelectric random access memory based cache which has symmetric read/write times and faster write times than either EEPROM or Flash memory.
摘要翻译：结合非易失性存储器阵列的集成电路存储器件和与其整体集成在一起的相对较快的存取时间存储器高速缓存提高了页面中的整体访问时间，并为阅读操作提供了更快的周期时间。在特定实施例中，高速缓存可以被提供为静态随机存取存储器（“SRAM”）和作为铁电随机存取存储器提供的非易失性存储器阵列，其中在读取时，该行被缓存并且回写周期开始允许随后的页面读取发生得非常快。如果在页面访问中足够存储器阵列预充电可能会被隐藏，并且写入可以通过缓存写回或写入来实现。在替代实施例中，非易失性存储器阵列可以包括具有对称读/写时间和更快写入时间的SRAM缓存或基于铁电随机存取存储器的高速缓存的电可擦除只读存储器（“EEPROM”）或闪存比EEPROM或闪存。

8. 发明授权

US06249841B1 Integrated circuit memory device and method incorporating flash and ferroelectric random access memory arrays 失效
标题翻译：集成电路存储器件和并入闪存和铁电随机存取存储器阵列的方法
公开(公告)号：US06249841B1
公开(公告)日：2001-06-19
申请号：US09205538
申请日：1998-12-03
申请人： L. David Sikes , Michael Alwais , Donald G. Carrigan
发明人： L. David Sikes , Michael Alwais , Donald G. Carrigan
IPC分类号： G11C1112
CPC分类号： G11C11/22 , G11C11/005
摘要： An integrated circuit memory device and method incorporating Flash and ferroelectric random access memory arrays integrated on a common substrate. The present invention allows a relatively small amount of ferroelectric random access memory to mitigate many of the erase and write time disadvantages exhibited by current Flash technology devices. In particular, whether combined together as a single stand-alone memory device or embedded together as a portion of a processor, microcontroller or application specific integrated circuit (“ASIC”), a block of ferroelectric memory that is sized to match the largest sector of Flash memory can effectively compensate for the latter's slow erasure and write times.
摘要翻译：一种集成电路存储器件和方法，其集成在公共衬底上的闪存和铁电随机存取存储器阵列。本发明允许相对较少量的铁电随机存取存储器来减轻当前闪存技术设备所呈现的许多擦除和写入时间缺点。特别地，无论是作为单独的独立存储器件一起组合还是作为处理器，微控制器或专用集成电路（“ASIC”）的一部分嵌入在一起，一块铁电存储器的块，其大小适于匹配最大扇区闪存可以有效地补偿后者的缓慢擦除和写入时间。

9. 发明授权

US4345365A Method for fabricating an integrated circuit 失效
标题翻译：集成电路制造方法
公开(公告)号：US4345365A
公开(公告)日：1982-08-24
申请号：US194658
申请日：1980-10-06
申请人： Donald G. Carrigan
发明人： Donald G. Carrigan
IPC分类号： H01L21/339 , H01L21/768 , H01L21/22
CPC分类号： H01L29/66954 , H01L21/768
摘要： This invention pertains to an improved multilevel integrated circuit wherein a single layer of metal or other conductive material is used for interconnection and formation of the conductors and/or gate electrodes of one of the conductor layers. The multilevel integrated circuit of the present invention also includes a thick interlayer insulator which is located between this conductor/interconnect layer and the underlying substrate and lower level conductors to electrically isolate this layer of metal therefrom. The interlayer insulator is not required in the channel region of charge-coupled circuits.
摘要翻译：本发明涉及一种改进的多电平集成电路，其中使用单层金属或其它导电材料来互连和形成导体层之一的导体和/或栅电极。本发明的多电平集成电路还包括位于该导体/互连层与下层基板和下层导体之间的厚层间绝缘体，以将该金属层电绝缘。电荷耦合电路的沟道区不需要层间绝缘体。

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