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1. 发明授权

US08281219B2 Error correction code (ECC) circuit test mode 有权
标题翻译：纠错码（ECC）电路测试模式
公开(公告)号：US08281219B2
公开(公告)日：2012-10-02
申请号：US11840203
申请日：2007-08-16
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/42 , G11C2029/0409 , G11C2029/0411
摘要： An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.
摘要翻译：用于集成电路存储器的ECC电路和方法允许用户进入测试模式并选择特定位置以迫使任何存储器芯片上的已知故障，无论其是完全功能还是部分功能。额外的电路放置在现有缓冲器和驱动器已经定位的数据路径中，最大限度地减少了实施强制数据故障所需的额外速度损失或面积。在第一种通用方法中，在给定时间将逻辑零强制到所选数据线上。在第二种通用方法中，在给定时间将逻辑1强制到所选择的数据线上。

2. 发明申请

US20090077453A1 TECHNIQUE FOR REDUCING PARITY BIT-WIDTHS FOR CHECK BIT AND SYNDROME GENERATION FOR DATA BLOCKS THROUGH THE USE OF ADDITIONAL CHECK BITS TO INCREASE THE NUMBER OF MINIMUM WEIGHTED CODES IN THE HAMMING CODE H-MATRIX 有权
标题翻译：通过使用附加检查位置来增加数据块中的最小加权代码数量H-MATRIX的数据块，以减少检查位的奇偶位宽度和综合生成的技术
公开(公告)号：US20090077453A1
公开(公告)日：2009-03-19
申请号：US11855070
申请日：2007-09-13
申请人： Oscar Frederick Jones, JR.
发明人： Oscar Frederick Jones, JR.
IPC分类号： G06F11/00
CPC分类号： H03M13/19 , H03M13/618 , H03M13/6502 , H03M13/6561
摘要： A technique for reducing parity bit-widths for check bit and syndrome generation through the use of additional check bits to increase the number of minimum weighted codes in the Hamming Code H-Matrix. The technique of the present invention may be implemented while adding no additional correction/detection capability, in order to reduce the number of data bits that are used for each check bit/syndrome generation and to reduce the width of the parity generating circuitry.
摘要翻译：一种用于通过使用附加校验位来减少校验位和校正子生成的校验位宽度以增加汉明码H矩阵中的最小加权码的数量的技术。本发明的技术可以在不添加额外的校正/检测能力的情况下实现，以便减少用于每个校验位/校正子生成的数据位的数量并减小奇偶生成电路的宽度。

3. 发明申请

US20090049350A1 ERROR CORRECTION CODE (ECC) CIRCUIT TEST MODE 有权
标题翻译：错误校正码（ECC）电路测试模式
公开(公告)号：US20090049350A1
公开(公告)日：2009-02-19
申请号：US11840203
申请日：2007-08-16
申请人： Michael C. Parris , Oscar Frederick Jones, JR.
发明人： Michael C. Parris , Oscar Frederick Jones, JR.
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/42 , G11C2029/0409 , G11C2029/0411
摘要： An ECC circuit and method for an integrated circuit memory allows a user to enter a test mode and select a specific location to force a known failure on any memory chip, whether it is fully functional or partially functional. Additional circuitry is placed in the data path where existing buffers and drivers are already located, minimizing any additional speed loss or area penalty required to implement the forced data failure. In a first general method, a logic zero is forced onto a selected data line at a given time. In a second general method, a logic one is forced onto a selected data line at a given time.
摘要翻译：用于集成电路存储器的ECC电路和方法允许用户进入测试模式并选择特定位置以迫使任何存储器芯片上的已知故障，无论其是完全功能还是部分功能。额外的电路放置在现有缓冲器和驱动器已经定位的数据路径中，最大限度地减少了实施强制数据故障所需的额外速度损失或面积。在第一种通用方法中，在给定时间将逻辑零强制到所选数据线上。在第二种通用方法中，在给定时间将逻辑1强制到所选择的数据线上。

4. 发明授权

US06732305B2 Test interface for verification of high speed embedded synchronous dynamic random access memory (SDRAM) circuitry 有权
标题翻译：用于验证高速嵌入式同步动态随机存取存储器（SDRAM）电路的测试接口
公开(公告)号：US06732305B2
公开(公告)日：2004-05-04
申请号：US09848800
申请日：2001-05-04
申请人： Oscar Frederick Jones, Jr. , Michael C. Parris
发明人： Oscar Frederick Jones, Jr. , Michael C. Parris
IPC分类号： G11C2900
CPC分类号： G11C29/56012 , G11C11/401 , G11C29/48 , G11C2029/0401 , G11C2029/5602
摘要： An integrated and constantly enabled on-chip test interface for use in verifying the functionality of high speed embedded memories such as synchronous dynamic random access memories (“SDRAM”) which allows for the utilization of existing, relatively low speed, (and hence low cost), testers to perform the testing. The interface allows for the verification of an embedded memory macro design utilizing a test interface which includes the memory macro and separate on-chip test circuitry so that half-rate, narrow word, input signals from a tester can perform all memory macro operations across the breadth of a wide memory macro input/output (“I/O”) architecture. The on-chip test circuitry may also include a synchronizing circuit to minimize skew between the external clock and the data output from the test chip.
摘要翻译：一种集成且不断启用的片上测试接口，用于验证高速嵌入式存储器的功能，例如同步动态随机存取存储器（“SDRAM”），其允许利用现有的，相对较低的速度（并且因此低成本），测试人员进行测试。该接口允许使用包括存储器宏和单独的片上测试电路的测试接口来验证嵌入式存储器宏设计，使得来自测试者的半速率，窄字，输入信号可以执行所有存储器宏操作宽的内存宏输入/输出（“I / O”）架构的宽度。片上测试电路还可以包括同步电路，以最小化外部时钟与从测试芯片输出的数据之间的偏差。

5. 发明授权

US06657461B2 System and method for high speed integrated circuit device testing utilizing a lower speed test environment 有权
标题翻译：利用低速测试环境进行高速集成电路设备测试的系统和方法
公开(公告)号：US06657461B2
公开(公告)日：2003-12-02
申请号：US09815146
申请日：2001-03-22
申请人： Oscar Frederick Jones, Jr. , Michael C. Parris
发明人： Oscar Frederick Jones, Jr. , Michael C. Parris
IPC分类号： G11C1300
CPC分类号： G01R31/31922 , G01R31/318505 , G01R31/318511
摘要： A system and method for low cost testing of integrated circuit devices at their rated speed during wafer probe testing while input signals to, and output signals from, the device may be operated at a lower speed. In the exemplary embodiment disclosed, a probe pad is used to enable a special test mode. When enabled, the on-chip clock generator enables a clock frequency doubler. The frequency doubler generates a 2× frequency clock from the 1× frequency external clock signals (two 1× clock phases with a 90 degree phase shift between the two clocks). The first phase of the clock uses the CLK input of the device and the second phase uses the device's CKE input.
摘要翻译：在晶圆探针测试期间以集成电路器件的额定速度进行低成本测试的系统和方法，同时可以以较低的速度操作来自器件的输入信号和输出信号。在所公开的示例性实施例中，探针焊盘用于实现特殊测试模式。当使能时，片上时钟发生器使时钟频率倍增。倍频器从1x频率外部时钟信号（两个1x时钟相位在两个时钟之间具有90度相移）产生2x频率时钟。时钟的第一阶段使用器件的CLK输入，第二阶段使用器件的CKE输入。

6. 发明授权

US06622198B2 Look-ahead, wrap-around first-in, first-out integrated (FIFO) circuit device architecture 失效
标题翻译：先进的，先进先出的集成（FIFO）电路设备架构
公开(公告)号：US06622198B2
公开(公告)日：2003-09-16
申请号：US09815148
申请日：2001-03-22
申请人： Oscar Frederick Jones, Jr.
发明人： Oscar Frederick Jones, Jr.
IPC分类号： G06F1200
CPC分类号： G06F5/10
摘要： A method for loading an integrated circuit FIFO at extremely high operating frequencies includes providing N logical locations, providing N+1 transparent latch stages, and providing N+1 write pointers, wherein two write pointers are contemporaneously enabled during a FIFO load operation. The method can be extended to enable three or more write pointers for even higher frequency operation.
摘要翻译：用于以极高工作频率加载集成电路FIFO的方法包括提供N个逻辑位置，提供N + 1个透明锁存级，并提供N + 1个写指针，其中两个写指针在FIFO加载操作期间同时启用。该方法可以扩展以使三个或更多个写指针用于更高频率的操作。

7. 发明授权

US06289413B1 Cached synchronous DRAM architecture having a mode register programmable cache policy 有权
标题翻译：具有模式寄存器可编程高速缓存策略的缓存同步DRAM架构
公开(公告)号：US06289413B1
公开(公告)日：2001-09-11
申请号：US09360373
申请日：1999-10-15
申请人： Jim L. Rogers , Steven W. Tomashot , David W. Bondurant , Oscar Frederick Jones, Jr. , Kenneth J. Mobley
发明人： Jim L. Rogers , Steven W. Tomashot , David W. Bondurant , Oscar Frederick Jones, Jr. , Kenneth J. Mobley
IPC分类号： G06F1206
CPC分类号： G06F12/0893 , G06F12/0804
摘要： A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.
摘要翻译：具有多存储体架构和可编程高速缓存策略的高速缓存的同步动态随机存取存储器（高速缓存的SDRAM）装置包括同步动态随机存取存储器（SDRAM）存储体，同步静态可随机寻址行寄存器，选择逻辑选通电路和模式寄存器，用于在写周期期间以与标准SDRAM的正常操作模式相对应的写传输模式来操作缓存的SDRAM，并且在写周期期间根据备用操作模式在无写传输模式下操作，从而分别在第一和第二缓存策略下运行。 SDRAM包括用于选择存储体阵列中的一行数据的行解码器，用于锁存由行解码器选择的数据行的读出放大器，以及用于选择该行数据的期望列的同步列选择器。行寄存器存储由读出放大器锁存的一行数据，并且设置在读出放大器和行寄存器之间的选择逻辑选通电路根据特定的同步，有选择地将存在于位线上的数据行写入行寄存器执行内存操作。

8. 再颁专利

USRE44726E1 Data inversion register technique for integrated circuit memory testing 有权
标题翻译：用于集成电路存储器测试的数据反转寄存器技术
公开(公告)号：USRE44726E1
公开(公告)日：2014-01-21
申请号：US13313792
申请日：2011-12-07
申请人： Michael C. Parris , Oscar Frederick Jones, Jr.
发明人： Michael C. Parris , Oscar Frederick Jones, Jr.
IPC分类号： G11C29/00 , H04L1/00 , G11C7/00
CPC分类号： G01R31/31713 , G11C29/10 , G11C29/56 , G11C2029/0409
摘要： A data inversion register technique for integrated circuit memory testing in which data input signals are selectively inverted in a predetermined pattern to maximize the probability of identifying failures during testing. In accordance with the technique of the present invention, on predetermined input/outputs (I/Os,) data inputs may be inverted to create a desired test pattern (such as data stripes) which are “worst case” for I/O circuitry or column stripes which are “worst case” for memory arrays. A circuit in accordance with the technique of the present invention then matches the pattern for the data out path, inverting the appropriate data outputs to obtain the expected tester data. In this way, the test mode is transparent to any memory tester.
摘要翻译：一种用于集成电路存储器测试的数据反转寄存器技术，其中数据输入信号以预定模式选择性地反转，以最大化在测试期间识别故障的可能性。根据本发明的技术，在预定的输入/输出（I / O））数据输入可以被反转以创建对于I / O电路是“最坏情况”的期望的测试图案（诸如数据条纹），或者列条纹是存储器阵列的“最坏情况”。根据本发明的技术的电路然后匹配数据输出路径的模式，反转适当的数据输出以获得预期的测试器数据。这样，测试模式对任何记忆测试仪都是透明的。

9. 发明申请

US20090237162A1 LOW SKEW DIFFERENTIAL AMPLIFIER USING TAIL VOLTAGE REFERENCE AND TAIL FEEDBACK 有权
标题翻译：低电压差分放大器，采用尾电压参考和尾波反馈
公开(公告)号：US20090237162A1
公开(公告)日：2009-09-24
申请号：US12053401
申请日：2008-03-21
申请人： Oscar Frederick Jones, JR.
发明人： Oscar Frederick Jones, JR.
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/3022 , H03F2203/30099 , H03F2203/30132 , H03F2203/45506 , H03F2203/45726
摘要： Using the tail level referencing for an inverter stage immediately following a differential amplifier provides trip point tracking with the variations in magnitude of the output level swings on the differential amplifier stage output over the operating range of the circuit. When the tail voltage increases and the VOL of the differential stage increases, the trip point of the receiving inverter also increases. When the tail voltage decreases and the VOL of the differential amplifier goes lower, the trip point of the inverter decreases. An additional benefit is provided by the tail connection to the inverter. Faster switching of current from the right side to the left side of the differential amplifier occurs due to the tail node voltage being raised momentarily by a transistor in the inverter stage when the input of the inverter stage transitions high.
摘要翻译：使用紧跟在差分放大器之后的逆变器级的尾部电平参考，提供了跳变点跟踪，并且在电路的工作范围内差分放大器级输出上的输出电平摆幅幅度的变化。当尾电压增加且差动级的VOL增加时，接收逆变器的跳变点也增加。当尾电压降低，差分放大器的VOL变低时，变频器的跳变点减小。通过与逆变器的尾部连接提供额外的好处。当逆变器级的输入转变为高电平时，由于在逆变器级中的晶体管的瞬态地引起尾部节点电压，所以发生从差动放大器的右侧到左侧的电流的更快的切换。

10. 发明授权

US07583142B1 Low skew differential amplifier using tail voltage reference and tail feedback 有权
标题翻译：低偏差差分放大器采用尾电压参考和尾部反馈
公开(公告)号：US07583142B1
公开(公告)日：2009-09-01
申请号：US12053401
申请日：2008-03-21
申请人： Oscar Frederick Jones, Jr.
发明人： Oscar Frederick Jones, Jr.
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/3022 , H03F2203/30099 , H03F2203/30132 , H03F2203/45506 , H03F2203/45726
摘要： Using the tail level referencing for an inverter stage immediately following a differential amplifier provides trip point tracking with the variations in magnitude of the output level swings on the differential amplifier stage output over the operating range of the circuit. When the tail voltage increases and the VOL of the differential stage increases, the trip point of the receiving inverter also increases. When the tail voltage decreases and the VOL of the differential amplifier goes lower, the trip point of the inverter decreases. An additional benefit is provided by the tail connection to the inverter. Faster switching of current from the right side to the left side of the differential amplifier occurs due to the tail node voltage being raised momentarily by a transistor in the inverter stage when the input of the inverter stage transitions high.
摘要翻译：使用紧跟在差分放大器之后的逆变器级的尾部电平参考，提供了跳变点跟踪，并且在电路的工作范围内差分放大器级输出上的输出电平摆幅幅度的变化。当尾电压增加且差动级的VOL增加时，接收逆变器的跳变点也增加。当尾电压降低，差分放大器的VOL变低时，变频器的跳变点减小。通过与逆变器的尾部连接提供额外的好处。当逆变器级的输入转变为高电平时，由于在逆变器级中的晶体管的瞬态地引起尾部节点电压，所以发生从差动放大器的右侧到左侧的电流的更快的切换。

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