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1. 发明授权

US06174763B1 Three-dimensional SRAM trench structure and fabrication method therefor 失效
标题翻译：三维SRAM沟槽结构及其制作方法
公开(公告)号：US06174763B1
公开(公告)日：2001-01-16
申请号：US08778609
申请日：1997-01-06
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Francis Roger White
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Francis Roger White
IPC分类号： H01L218244
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/78642 , Y10S257/903
摘要： A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors (“FETs”) buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed, A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.
摘要翻译：阐述了一种三维五晶体管沟槽结构及其制造方法。 SRAM沟槽结构包括埋在单个沟槽内的四个场效应晶体管（“FET”）。具体地说，两个FET位于沟槽的两个侧壁中的每个侧壁处，一个FET设置在另一个FET的每个侧壁的上方。同轴布线使沟槽内的FET交叉耦合，从而形成包括用于SRAM单元的存储触发器的一对交叉耦合的反相器，第五个I / O晶体管设置在沟槽结构的顶部，并且便于访问触发器。还阐述了SRAM沟槽结构的具体细节及其制造方法。

2. 发明授权

US5670803A Three-dimensional SRAM trench structure and fabrication method therefor 失效
标题翻译：三维SRAM沟槽结构及其制作方法
公开(公告)号：US5670803A
公开(公告)日：1997-09-23
申请号：US386721
申请日：1995-02-08
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Francis Roger White
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Francis Roger White
IPC分类号： H01L21/8244 , H01L21/84 , H01L27/11 , H01L27/12 , H01L29/786 , H01L23/485 , H01L23/528 , H01L29/41
CPC分类号： H01L27/11 , H01L21/84 , H01L27/1104 , H01L27/1203 , H01L29/78642 , Y10S257/903
摘要： A three-dimensional five transistor SRAM trench structure and fabrication method therefor are set forth. The SRAM trench structure includes four field-effect transistors ("FETs") buried within a single trench. Specifically, two FETs are located at each of two sidewalls of the trench with one FET being disposed above the other FET at each sidewall. Coaxial wiring electrically cross-couples the FETs within the trench such that a pair of cross-coupled inverters comprising the storage flip-flop for the SRAM cell is formed. A fifth, I/O transistor is disposed at the top of the trench structure, and facilitates access to the flip-flop. Specific details of the SRAM trench structure, and fabrication methods therefor are also set forth.
摘要翻译：阐述了一种三维五晶体管沟槽结构及其制造方法。 SRAM沟槽结构包括埋在单个沟槽内的四个场效应晶体管（“FET”）。具体地说，两个FET位于沟槽的两个侧壁中的每个侧壁处，一个FET设置在另一个FET的每个侧壁的上方。同轴布线使沟槽内的FET交叉耦合，从而形成包括用于SRAM单元的存储触发器的一对交叉耦合的反相器。第五个I / O晶体管设置在沟槽结构的顶部，并且便于接触到触发器。还阐述了SRAM沟槽结构的具体细节及其制造方法。

3. 发明授权

US5786628A Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging 失效
标题翻译：用于将薄层连接到单片电子模块表面和相关模块封装的方法和工件
公开(公告)号：US5786628A
公开(公告)日：1998-07-28
申请号：US951663
申请日：1997-10-16
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L23/06 , H01L23/02
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.
摘要翻译：一种具有附接到侧表面的单独形成的薄膜层的制造方法和所得到的单片电子模块。该制造方法包括提供由堆叠的集成电路芯片组成的电子模块。在用于将薄膜层附着到电子模块的临时支架上分开形成薄膜层。所公开的技术还可以用于将可包括有源电路的插入件附接到电子模块。阐述了制造方法，所得到的多芯片封装以及各种薄膜结构的具体细节。

4. 发明授权

US5719438A Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging 失效
公开(公告)号：US5719438A
公开(公告)日：1998-02-17
申请号：US469090
申请日：1995-06-06
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , John Edward Cronin , Wayne John Howell , James Marc Leas , David Jacob Perlman
IPC分类号： H01L21/98 , H01L23/498 , H01L25/065 , H01L25/18 , H01L23/02 , H01L23/04
CPC分类号： H01L25/50 , H01L23/49827 , H01L25/0652 , H01L25/0657 , H01L25/18 , H01L2224/16145 , H01L2224/16227 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/49107 , H01L2224/49109 , H01L2224/73265 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2225/06555 , H01L2225/06572 , H01L2225/06582 , H01L2225/06586 , H01L2225/06589 , H01L24/48 , H01L24/49 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/01079 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15311 , H01L2924/15312 , H01L2924/1532 , H01L2924/16152 , H01L2924/16195 , H01L2924/30107
摘要： A fabrication method and resultant monolithic electronic module having a separately formed thin-film layer attached to a side surface. The fabrication method includes providing an electronic module composed of stacked integrated circuit chips. A thin-film layer is separately formed on a temporary support which is used to attach the thin-film layer to the electronic module. The disclosed techniques may also be used for attaching an interposer, which may include active circuity, to an electronic module. Specific details of the fabrication method, resulting multichip packages, and various thin-film structures are set forth.

5. 发明授权

US5670428A Semiconductor chip kerf clear method and resultant semiconductor chip and electronic module formed from the same 失效
标题翻译：半导体芯片切片方法及其相结合的半导体芯片和电子模块
公开(公告)号：US5670428A
公开(公告)日：1997-09-23
申请号：US422029
申请日：1995-04-13
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
IPC分类号： H01L25/18 , H01L21/02 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04 , H01L21/60
CPC分类号： H01L25/50 , H01L24/24 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/14
摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
摘要翻译：一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。芯片金属化存在于切口区域内。使用光刻工艺来保护仅暴露切口区域的晶片。接下来，蚀刻晶片，从切口区域清除芯片金属化。然后切割晶片，并且将芯片堆叠以形成单片电子模块。处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

6. 发明授权

US5804464A Semiconductor chip kerf clear method for forming semiconductor chips and electronic module therefore 失效
标题翻译：因此，用于形成半导体芯片和电子模块的半导体芯片切屑清除方法
公开(公告)号：US5804464A
公开(公告)日：1998-09-08
申请号：US847081
申请日：1997-05-01
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
IPC分类号： H01L25/18 , H01L21/02 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04 , H01L21/44
CPC分类号： H01L25/50 , H01L24/24 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/14
摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
摘要翻译：一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。芯片金属化存在于切口区域内。使用光刻工艺来保护仅暴露切口区域的晶片。接下来，蚀刻晶片，从切口区域清除芯片金属化。然后切割晶片，并且将芯片堆叠以形成单片电子模块。处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

7. 发明授权

US5686843A Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module 失效
标题翻译：多芯片模块中半导体器件芯片的老化应力和同步测试方法和设备
公开(公告)号：US5686843A
公开(公告)日：1997-11-11
申请号：US497126
申请日：1995-06-30
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Dennis Charles Dubois , Wayne John Howell , Gordon Arthur Kelley, Jr. , Christopher Paul Miller , David Jacob Perlman , Gustav Schrottke , Edmund Juris Sprogis , Jody John VanHorn
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Dennis Charles Dubois , Wayne John Howell , Gordon Arthur Kelley, Jr. , Christopher Paul Miller , David Jacob Perlman , Gustav Schrottke , Edmund Juris Sprogis , Jody John VanHorn
IPC分类号： G01R31/26 , G01R1/04 , G01R31/28 , H01L21/66 , H01L25/00 , G01R31/02
CPC分类号： G01R31/2863 , G01R1/0483 , G01R31/2851 , G01R31/2886 , G01R31/2889 , H01L2924/0002
摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.
摘要翻译：阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。通过将临时互连线连接到多芯片模块的访问表面来实现测试。该临时互连布线使模块内的至少一些半导体器件芯片电互连。在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。此后，使用临时互连布线发生多芯片模块内的半导体芯片的老化强度和同时测试。描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

8. 发明授权

US5644162A Semiconductor chip having chip metal layer and transfer metal layer composed of same metal, and corresponding electronic module 失效
标题翻译：具有芯片金属层和由相同金属组成的转移金属层的半导体芯片及相应的电子模块
公开(公告)号：US5644162A
公开(公告)日：1997-07-01
申请号：US660556
申请日：1996-06-10
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Timothy Harrison Daubenspeck , Wayne John Howell
IPC分类号： H01L25/18 , H01L21/02 , H01L21/301 , H01L21/3205 , H01L21/822 , H01L21/98 , H01L23/52 , H01L25/065 , H01L25/07 , H01L27/00 , H01L27/04 , H01L23/48
CPC分类号： H01L25/50 , H01L24/24 , H01L25/0657 , H01L2225/06524 , H01L2225/06541 , H01L2225/06551 , H01L2924/14
摘要： A fabrication method including a semiconductor chip kerf clear process and a resulting semiconductor chip and electronic module formed thereby. The fabrication method includes providing a wafer comprising a plurality of integrated circuit chips having kerf regions between them. Chip metallization is present within the kerf regions. A photolithography process is used to protect the wafer exposing only the kerf regions. Next, the wafer is etched, clearing the chip metallization from the kerf regions. The wafer is then diced and the chips are stacked to form a monolithic electronic module. A side surface of the electronic module is processed to expose transfer metals extending thereto, thereby facilitating electrical connection to the chips within the electronic module. Specific details of the fabrication method, resulting integrated circuit chips and monolithic electronic module are set forth.
摘要翻译：一种制造方法，包括半导体芯片切痕工艺以及由此形成的半导体芯片和电子模块。制造方法包括提供包括多个集成电路芯片的晶片，其中它们之间具有切口区域。芯片金属化存在于切口区域内。使用光刻工艺来保护仅暴露切口区域的晶片。接下来，蚀刻晶片，从切口区域清除芯片金属化。然后切割晶片，并且将芯片堆叠以形成单片电子模块。处理电子模块的侧表面以暴露延伸到其上的转移金属，从而便于与电子模块内的芯片的电连接。阐述了制造方法的具体细节，所得到的集成电路芯片和单片电子模块。

9. 发明授权

US5923181A Methods and apparatus for burn-in stressing and simultaneous testing of semiconductor device chips in a multichip module 失效
标题翻译：多芯片模块中半导体器件芯片的老化应力和同步测试方法和设备
公开(公告)号：US5923181A
公开(公告)日：1999-07-13
申请号：US840041
申请日：1997-04-24
申请人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Dennis Charles Dubois , Wayne John Howell , Gordon Arthur Kelley, Jr. , Christopher Paul Miller , David Jacob Perlman , Gustav Schrottke , Edmund Juris Sprogis , Jody John VanHorn
发明人： Kenneth Edward Beilstein, Jr. , Claude Louis Bertin , Dennis Charles Dubois , Wayne John Howell , Gordon Arthur Kelley, Jr. , Christopher Paul Miller , David Jacob Perlman , Gustav Schrottke , Edmund Juris Sprogis , Jody John VanHorn
IPC分类号： G01R31/26 , G01R1/04 , G01R31/28 , H01L21/66 , H01L25/00 , G01R31/02
CPC分类号： G01R31/2863 , G01R1/0483 , G01R31/2851 , G01R31/2886 , G01R31/2889 , H01L2924/0002
摘要： Methods and apparatus are set forth for burn-in stressing and simultaneous testing of a plurality of semiconductor device chips laminated together in a stack configuration to define a multichip module. Testing is facilitated by connecting temporary interconnect wiring to an access surface of the multichip module. This temporary interconnect wiring electrically interconnects at least some semiconductor device chips within the module. Prior to burn-in stressing and testing, a separate electrical screening step occurs to identify any electrical defect in the connection between the temporary interconnect wiring and the multichip module. If an electrical defect is identified, various techniques for removing or isolating the defect are presented. Thereafter, burn-in stressing and simultaneous testing of the semiconductor chips within the multichip module occurs using the temporary interconnect wiring. Various alignment and test fixtures are described for facilitating this burn-in and simultaneous testing of the semiconductor chips within the multichip module.
摘要翻译：阐述了以堆叠配置层叠在一起的多个半导体器件芯片的老化应力和同时测试方法和装置，以限定多芯片模块。通过将临时互连线连接到多芯片模块的访问表面来实现测试。该临时互连布线使模块内的至少一些半导体器件芯片电互连。在老化应力和测试之前，会发生单独的电气筛选步骤，以识别临时互连线路和多芯片模块之间的连接中的任何电气缺陷。如果识别出电气缺陷，则提出了用于去除或隔离缺陷的各种技术。此后，使用临时互连线路进行多芯片模块内的半导体芯片的老化强度和同时测试。描述了各种对准和测试夹具，以便于该多芯片模块内的半导体芯片的老化和同时测试。

10. 发明授权

US4092548A Substrate bias modulation to improve mosfet circuit performance 失效
标题翻译：衬底偏置调制，以提高MOSFET的电路性能
公开(公告)号：US4092548A
公开(公告)日：1978-05-30
申请号：US777793
申请日：1977-03-15
申请人： Kenneth Edward Beilstein, Jr. , Harish Narandas Kotecha
发明人： Kenneth Edward Beilstein, Jr. , Harish Narandas Kotecha
IPC分类号： H01L21/822 , H01L21/761 , H01L21/8236 , H01L27/04 , H01L27/088 , H03K17/687 , H03K19/094 , H03K19/0944 , H03K19/40 , H01L29/78 , H03K3/353
CPC分类号： H01L21/761 , H01L27/0883 , H03K19/09443
摘要： A load device characteristic is improved for a static inverter by reducing the load device threshold voltage as the output voltage increases from its initial value. The circuit structure to accomplish this is an isolated substrate within which the FET load device is located, that substrate being connected to an inverter circuit for raising the voltage of the substrate as the source potential increases for the preferred depletion mode load device. The particular circuit is a two-stage inverter, the first stage being a modulating signal source, the output of the first stage inverter being connected to the isolated substrate of the FET load for a second inverter, so that the FET load device for the second stage inverter has its substrate modulated so that the magnitude of the substrate potential changes at a faster rate than does the source potential. This tracking of the potential of the substrate with respect to the potential of the source of the device decreases the threshold voltage as the output voltage of the second stage increases.
摘要翻译：当输出电压从初始值增加时，通过减少负载装置阈值电压，对于静态逆变器，负载装置特性得到改善。实现这一点的电路结构是FET负载装置所在的隔离衬底，当优选耗尽模式负载装置的电位电位增加时，衬底连接到用于提高衬底的电压的逆变器电路。特定电路是两级反相器，第一级是调制信号源，第一级反相器的输出端连接到用于第二反相器的FET负载的隔离衬底，使得用于第二级的FET负载装置其基极调制，使得衬底电位的幅度以比源电位更快的速率变化。当第二级的输出电压增加时，衬底相对于器件的电位的电位的跟踪降低阈值电压。

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