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    • 3. 发明授权
      US5880988A Reference potential for sensing data in electronic storage element 失效
    • Reference potential for sensing data in electronic storage element
    • 电子存储元件中感应数据的参考电位
    • US5880988A
    • 1999-03-09
    • US893797
    • 1997-07-11
    • Claude Louis Bertin , John Atkinson Fifield , Russell James Houghton , Christopher Paul Miller , William Robert Patrick Tonti
    • Claude Louis Bertin , John Atkinson Fifield , Russell James Houghton , Christopher Paul Miller , William Robert Patrick Tonti
    • G11C11/401 , G11C7/14 , G11C5/06
    • G11C7/14
    • A column of an integrated memory circuit includes two bit lines each with a right half and a left half and a plurality of similar memory cells connected to each half of each bit line. One of the memory cells connected to each line is used as a reference and the other cells are used for data storage. Each half of each bit line is connected to a sense node of a sense amplifier latch through an independently controlled transistor switch. To read the data from the first half of the first bit line, the transistors connecting the first half of the first bit line to the sense node is turned on and the transistor connecting the second half of the first bit line to the sense node is turned off. Both transistor switches connecting respective halves of the other bit line to the other sense node are turned on. Each half of each bit line includes approximately the same effective load. The load applied to the first sense node is thus about half of the load applied to the second sense node. Access switches are opened to access the value stored in the data memory element and the reference data element and the resulting potential in the bit lines are significantly different whether the same value is stored or not, due to the different loads. Preferably, the output of the memory elements is selected so that the reference potential is about midway between the potential in a bit line half connected to a memory element storing a high value and a low value.
    • 集成存储器电路的列包括两个位线，每个位线具有连接到每个位线的每一半的右半部分和左半部分以及多个相似的存储器单元。 连接到每条线的存储器单元之一用作参考，其他单元用于数据存储。 每个位线的每一半通过独立控制的晶体管开关连接到读出放大器锁存器的感测节点。 为了读取来自第一位线的前半部分的数据，将第一位线的前半部分连接到感测节点的晶体管导通，并且将第一位线的第二半部分连接到感测节点的晶体管被​​转换 关闭 将另一个位线的相应两半连接到另一个感测节点的两个晶体管开关导通。 每个位线的每一半包括大致相同的有效负载。 因此，施加到第一感测节点的负载大约是施加到第二感测节点的负载的一半。 打开访问开关以访问存储在数据存储器元件中的值和参考数据元素，并且由于不同的负载，位线中产生的电位是否与存储相同的值是显着不同的。 优选地，存储器元件的输出被选择为使得参考电位在连接到存储高值和低值的存储元件的位线半部中的电位之间的大约中间。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 4. 发明授权
      US5809528A Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory 失效
    • Method and circuit for a least recently used replacement mechanism and invalidated address handling in a fully associative many-way cache memory
    • 用于最近最近使用的替换机制的方法和电路以及完全关联的多路高速缓冲存储器中的无效地址处理
    • US5809528A
    • 1998-09-15
    • US772819
    • 1996-12-24
    • Christopher Paul Miller , Dale Edward Pontius
    • Christopher Paul Miller , Dale Edward Pontius
    • G06F12/12 , G06F12/00 , G06F13/00
    • G06F12/126
    • An architecture and method of implementing an invalid data handling least recently used replacement mechanism in a cache memory system is provided that includes a first register stack, a second register stack and stack control logic. The first register stack includes registers for holding entry address information. The stack control logic includes logic for inhibiting the placement of invalidated entry addresses into a Most Recently Used register in the first register stack and directs that such invalidated entry addresses be input into the second register. The stack control logic further directs that any new entry addresses be placed in the first register stack where invalidated entry addresses has resided. A counter keeps count of the number of invalidated entry addresses input into the second register stack and toggles a multiplexer at a Least Recently Used Entry output of the first register stack to select as its output, the output of the second register stack. In this manner, invalidated entry address are output from the cache through the second register stack while valid Least Recently Used entry addresses remain in the first register stack.
    • 提供了一种在高速缓冲存储器系统中实现无效数据处理最近最少使用的替换机制的架构和方法，其包括第一寄存器堆栈，第二寄存器堆栈和堆栈控制逻辑。 第一寄存器堆栈包括用于保存入口地址信息的寄存器。 堆栈控制逻辑包括用于禁止将无效输入地址放置到第一寄存器堆栈中的最近使用的寄存器中的逻辑，并指示这些无效输入地址被输入到第二寄存器。 堆栈控制逻辑进一步指示任何新的入口地址被放置在无效输入地址所在的第一个寄存器堆栈中。 计数器保持输入到第二寄存器堆栈的无效输入地址的数量，并将多路复用器切换到第一寄存器堆栈的最近最近使用的输入输出，以选择第二寄存器堆栈的输出作为其输出。 以这种方式，通过第二寄存器堆栈从高速缓存输出无效的入口地址，而有效的最近使用的入口地址保留在第一寄存器堆栈中。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 6. 发明授权
      US5787457A Cached synchronous DRAM architecture allowing concurrent DRAM operations 失效
    • Cached synchronous DRAM architecture allowing concurrent DRAM operations
    • 缓存的同步DRAM架构允许并发DRAM操作
    • US5787457A
    • 1998-07-28
    • US731790
    • 1996-10-18
    • Christopher Paul Miller , Jim Lewis Rogers , Steven William Tomashot
    • Christopher Paul Miller , Jim Lewis Rogers , Steven William Tomashot
    • G11C11/407 , G06F12/08 , G11C7/10 , G11C11/401
    • G11C7/103 , G06F12/0893 , G11C7/1072
    • A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture includes a synchronous dynamic random access memory (SDRAM) bank including a row decoder coupled to a memory bank array for selecting a row of data in the memory bank array, sense amplifiers coupled to the memory bank array via bit lines for latching the row of data selected by the row decoder, and a synchronous column select means for selecting a desired column of the row of data. A randomly addressable row register stores a row of data latched by the sense amplifiers. A select logic gating means, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations of the cached SDRAM being performed. Data to be input into the cached SDRAM during a Write operation is received by the sense amplifiers and written into the memory bank array. Data to be output from the cached SDRAM during a Read command is read out only from the row register, the row of data contained in the row register first having been read from the memory bank array to the sense amplifiers and then selectively gated to the row register in accordance with the particular synchronous memory operations.
    • 具有多存储体架构的高速缓存的同步动态随机存取存储器（高速缓存的SDRAM）装置包括同步动态随机存取存储器（SDRAM）存储体，其包括耦合到存储体阵列的行解码器，用于选择存储体阵列中的一行数据 ，经由位线耦合到存储体阵列的读出放大器，用于锁存由行解码器选择的数据行;以及同步列选择装置，用于选择数据行行的期望列。 可随机寻址的行寄存器存储由读出放大器锁存的一行数据。 设置在感测放大器和行寄存器之间的选择逻辑门控装置根据所执行的缓存的SDRAM的特定同步存储器操作，有选择地将出现在位线上的数据行门控地写入行寄存器。 在写操作期间要输入缓存的SDRAM的数据由读出放大器接收并写入存储体阵列。 在Read命令期间从缓存的SDRAM输出的数据仅从行寄存器读出，首先将包含在行寄存器中的数据行从存储体阵列读取到读出放大器，然后选择性地选通到行 根据特定的同步存储器操作进行注册。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 7. 发明授权
      US06455568B2 Combination therapy for inhibiting sphincter incontinence 失效
    • Combination therapy for inhibiting sphincter incontinence
    • 用于抑制括约肌失禁的组合疗法
    • US06455568B2
    • 2002-09-24
    • US09896227
    • 2001-06-29
    • Simon Nicholas Jenkins , Christopher Paul Miller
    • Simon Nicholas Jenkins , Christopher Paul Miller
    • A61K31405
    • A61K9/2059 , A61K9/2018 , A61K9/2054 , A61K45/06
    • This invention comprises methods of inducing or maintaining sphincter continence, or inhibiting or alleviating incontinence, in a mammal comprising administration of a compound of the formulae I or II: wherein Z is a moiety selected from the group of: wherein: R1 is selected from H, OH or the C1-C12 esters or C1-C12 alkyl ethers thereof, benzyloxy, or halogens; or C1-C4 halogenated ethers including trifluoromethyl ether and trichloromethyl ether; R2, R3, R4, R5, and R6 are H, OH or C1-C12 esters or C1-C12 alkyl ethers thereof, halogens, or C1-C4 halogenated ethers, cyano, C1-C6 alkyl, or trifluoromethyl, with the proviso that, when R1 is H, R2 is not OH; Y is the moiety: R7 and R8 are alkyl or concatenated together to form an optionally substituted, nitrogen-containing ring; or a pharmaceutically acceptable salt thereof.
    • 本发明包括在哺乳动物中诱导或维持括约肌紧张或抑制或减轻尿失禁的方法，包括施用式I或II化合物：其中Z是选自以下的部分：其中：R1选自H ，OH或其C1-C12酯或其C1-C12烷基醚，苄氧基或卤素; 或包括三氟甲基醚和三氯甲基醚的C 1 -C 4卤代醚; R2，R3，R4，R5和R6是H，OH或C1-C12酯或其C1-C12烷基醚，卤素或C1-C4卤代醚，氰基，C1-C6烷基或三氟甲基，条件是 当R1为H时，R2不为OH; Y是部分：R 7和R 8是烷基或连接在一起形成任选取代的含氮环; 或其药学上可接受的盐。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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