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    • 2. 发明授权
    • Buffer circuit
    • 缓冲电路
    • US6054876A
    • 2000-04-25
    • US118072
    • 1998-07-17
    • Masakiyo HorieHirofumi IsomuraTakuya Harada
    • Masakiyo HorieHirofumi IsomuraTakuya Harada
    • H03F3/30H03F3/45H03F3/68H03K19/0185H03K19/0175H03K17/687H03K19/003H03K19/094
    • H03F3/3032H03F3/45183H03K19/018521H03F2203/45641H03F2203/45674
    • A buffer circuit includes a signal input terminal and a signal output terminal. A first operational amplifier includes a differential amplifier circuit having an input transistor of an N-channel MOS type. The first operational amplifier has an inverting input terminal and an output terminal connected to each other. The first operational amplifier has a non-inverting input terminal connected to the signal input terminal. A second operational amplifier includes a differential amplifier circuit having an input transistor of a P-channel MOS type. The second operational amplifier has an inverting input terminal and an output terminal connected to each other. The second operational amplifier has a non-inverting input terminal connected to the signal input terminal. A first switching device operates for connecting the output terminal of the first operational amplifier to the signal output terminal when a voltage of an input signal applied to the signal input terminal is in a range where the first operational amplifier is operative. A second switching device operates for connecting the output terminal of the second operational amplifier to the signal output terminal when the voltage of the input signal applied to the signal input terminal is in a range where the second operational amplifier is operative.
    • 缓冲电路包括信号输入端和信号输出端。 第一运算放大器包括具有N沟道MOS型输入晶体管的差分放大器电路。 第一运算放大器具有彼此连接的反相输入端子和输出端子。 第一运算放大器具有连接到信号输入端的非反相输入端。 第二运算放大器包括具有P沟道MOS型输入晶体管的差分放大器电路。 第二运算放大器具有相互连接的反相输入端和输出端。 第二运算放大器具有连接到信号输入端的非反相输入端。 当施加到信号输入端的输入信号的电压处于第一运算放大器工作的范围时,第一开关装置用于将第一运算放大器的输出端连接到信号输出端。 当施加到信号输入端的输入信号的电压处于第二运算放大器工作的范围时,第二开关装置用于将第二运算放大器的输出端连接到信号输出端。
    • 5. 发明授权
    • Memory control apparatus for serial memory
    • 用于串行存储器的存储器控​​制装置
    • US06798707B2
    • 2004-09-28
    • US10234132
    • 2002-09-05
    • Akimasa NiwaTakuya HaradaTakayuki AonoShuji Agatsuma
    • Akimasa NiwaTakuya HaradaTakayuki AonoShuji Agatsuma
    • G11C700
    • G11C7/109G11C7/1078G11C16/32G11C2207/107G11C2216/30
    • A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.
    • 用于控制串行存储器中的存储器阵列的操作的存储器控​​制装置使用命令控制部分,用于将作为外部提供的串行数据集合接收的指令的位与一个时钟的相应的一系列周期相结合 信号,其中每组串行数据被格式化为在起始位之前的命令数据部分,由此检测起始位到移位寄存器的MSB级的移位,并用于终止向移位寄存器提供时钟信号, 从而消除了使用计数器电路。 检测到起始位移位到移位寄存器的MSB级之后的任何额外的时钟信号周期,从而可以可靠地消除接收到的时钟信号中由噪声引起的操作错误。
    • 8. 发明申请
    • A/D conversion device having input level shift and output correction function
    • 具有输入电平移位和输出校正功能的A / D转换装置
    • US20050168363A1
    • 2005-08-04
    • US11043192
    • 2005-01-27
    • Takuya Harada
    • Takuya Harada
    • H03M1/12H03M1/06H03M1/18H03M1/34
    • H03M1/181
    • In an A/D conversion device, one level shift circuit shifts an input voltage to the low potential side by Vt1, and another level shift circuit shifts the input voltage to the high potential side by Vt2. A multiplexer selects either of the shifted voltages to an A/D converter. In a correction mode, a correction data holding circuit holds values of reference voltages that are also A/D converted after being passed through the one level shift circuit and values of reference voltages that are A/D converted by being passed through the other level shift circuit, as correction values. A correction control circuit corrects the A/D converted value using the correction values.
    • 在A / D转换装置中,一个电平移位电路将输入电压移动到低电位侧Vt 1,另一个电平移位电路将输入电压移动到高电位侧Vt 2。 多路复用器选择移位电压中的任一个到A / D转换器。 在校正模式中,校正数据保持电路保持在通过一电平移位电路之后也进行A / D转换的参考电压的值和通过其他电平移位进行A / D转换的参考电压的值 电路,作为校正值。 校正控制电路使用校正值校正A / D转换值。
    • 9. 发明授权
    • Offset voltage correction circuit
    • 偏移电压校正电路
    • US6054887A
    • 2000-04-25
    • US112284
    • 1998-07-09
    • Masakiyo HorieTakuya Harada
    • Masakiyo HorieTakuya Harada
    • H03F3/34H03F1/30H03L5/00
    • H03F1/304
    • An offset voltage correction circuit for an operational amplifier (1) includes an offset voltage varying device (16, 17, 20, 21-23) for varying an offset voltage in the operational amplifier (1) in response to an offset voltage control value. A comparing device (25) operates for comparing an output voltage from the operational amplifier (1) with a prescribed reference voltage. A control device (19, 300) operates for outputting the offset voltage control value to the offset voltage varying device, for changing the offset voltage control value, for storing, in response to a result of the comparing by the comparing device (25), a digital signal representative of the offset voltage control value at which the output voltage from the operational amplifier (1) and the prescribed reference voltage are equal, and for correcting the offset voltage in the operational amplifier (1) in response to the stored digital signal.
    • 用于运算放大器(1)的偏移电压校正电路包括用于响应于偏移电压控制值改变运算放大器(1)中的偏移电压的偏移电压变化器件(16,17,20,21-23)。 比较装置(25)用于将来自运算放大器(1)的输出电压与规定的参考电压进行比较。 控制装置(19,300)用于将偏移电压控制值输出到偏移电压变化装置,用于改变偏移电压控制值,用于响应于比较装置(25)的比较结果存储, 表示来自运算放大器(1)和规定参考电压的输出电压相等的偏移电压控制值的数字信号,并且用于响应于所存储的数字信号来校正运算放大器(1)中的偏移电压 。
    • 10. 发明授权
    • Valuable threshold waveform shaping apparatus
    • 宝贵的阈值波形整形装置
    • US5841301A
    • 1998-11-24
    • US618620
    • 1996-03-20
    • Masakiyo HorieTakuya Harada
    • Masakiyo HorieTakuya Harada
    • G01D5/245G01D5/244G01R23/06H03K5/08H03K5/01
    • H03K5/086
    • A waveform shaping apparatus includes a comparing device for comparing a sensor output signal with a threshold voltage to convert the sensor output signal into a waveform shaped signal. The comparing device outputs the waveform shaped signal. The waveform shaping apparatus also includes a frequency-to-voltage converting device for generating the threshold voltage in response to a frequency of the output signal from the comparing device. In the frequency-to-voltage converting device, a clock signal is generated in response to the output signal from the comparing device. The clock signal has a period proportional to a period of the output signal from the comparing device. A counting device is operative for counting pulses in the clock signal generated by the clock signal generating device for every given period, and outputting a signal representing a counted pulse number depending on the frequency of the output signal from the comparing device. A D/A converting device is operative for converting the output signal from the counting device into a voltage signal which depends on the counted pulse number. The threshold voltage is generated in response to the voltage signal generated by the D/A converting device.
    • 波形整形装置包括比较装置,用于将传感器输出信号与阈值电压进行比较,以将传感器输出信号转换为波形形状信号。 比较装置输出波形整形信号。 波形整形装置还包括频率 - 电压转换装置,用于响应于来自比较装置的输出信号的频率产生阈值电压。 在频率 - 电压转换装置中,响应于来自比较装置的输出信号产生时钟信号。 时钟信号具有与比较装置的输出信号的周期成比例的周期。 计数装置用于对每个给定时间段由时钟信号产生装置产生的时钟信号中的脉冲进行计数,并根据来自比较装置的输出信号的频率输出表示计数脉冲数的信号。 D / A转换装置用于将来自计数装置的输出信号转换成取决于计数的脉冲数的电压信号。 响应于由D / A转换器产生的电压信号产生阈值电压。