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1. 发明授权

US06798707B2 Memory control apparatus for serial memory 失效
标题翻译：用于串行存储器的存储器控制装置
公开(公告)号：US06798707B2
公开(公告)日：2004-09-28
申请号：US10234132
申请日：2002-09-05
申请人： Akimasa Niwa , Takuya Harada , Takayuki Aono , Shuji Agatsuma
发明人： Akimasa Niwa , Takuya Harada , Takayuki Aono , Shuji Agatsuma
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1078 , G11C16/32 , G11C2207/107 , G11C2216/30
摘要： A memory control apparatus for controlling the operation of a memory array in a serial memory employs a command control section for registering the bits of an instruction which is received as an externally supplied set of serial data in conjunction with a corresponding series of cycles of a clock signal, with each set of serial data formatted as a command data portion preceded by a start bit, whereby the shifting of the start bit into the MSB stage of the shift register is detected and used to terminate supplying the clock signal to the shift register, thereby eliminating the use of a counter circuit. Any additional clock signal cycle following shifting of the start bit into the MSB stage of the shift register is detected, so that operating errors caused by noise in the received clock signal can be reliably eliminated.
摘要翻译：用于控制串行存储器中的存储器阵列的操作的存储器控制装置使用命令控制部分，用于将作为外部提供的串行数据集合接收的指令的位与一个时钟的相应的一系列周期相结合信号，其中每组串行数据被格式化为在起始位之前的命令数据部分，由此检测起始位到移位寄存器的MSB级的移位，并用于终止向移位寄存器提供时钟信号，从而消除了使用计数器电路。检测到起始位移位到移位寄存器的MSB级之后的任何额外的时钟信号周期，从而可以可靠地消除接收到的时钟信号中由噪声引起的操作错误。

2. 发明授权

US06798708B2 Memory controller and serial memory 失效
标题翻译：内存控制器和串行存储器
公开(公告)号：US06798708B2
公开(公告)日：2004-09-28
申请号：US10351311
申请日：2003-01-27
申请人： Akimasa Niwa , Takayuki Aono , Takuya Harada
发明人： Akimasa Niwa , Takayuki Aono , Takuya Harada
IPC分类号： G11C700
CPC分类号： G06F13/1668 , G11C7/1006 , G11C16/06
摘要： In a memory controller, a serial data including an instruction bit train with addition of a start bit, a clock signal, a chip enable signal, and a reset signal are inputted. During the active period in which the chip enable signal is being inputted, the serial data is stored depending on the clock signal and an enabling signal is generated based on the end timing of active period. Thereby, memory access is executed depending on contents of the instruction bit train. However, when the relevant apparatus is reset during the active period, generation of the enabling signal based on the end timing of the active period is inhibited.
摘要翻译：在存储器控制器中，输入包括添加起始位，时钟信号，芯片使能信号和复位信号的指令位列的串行数据。在输入芯片使能信号的活动期间，根据时钟信号存储串行数据，根据活动期间的结束时刻产生使能信号。由此，根据指令位列的内容执行存储器访问。然而，当有效期间相关装置复位时，基于活动期间的结束定时的使能信号的生成被禁止。

3. 发明授权

US06922711B2 Approximate calculator for non-linear function and map decoder using same 失效
标题翻译：用于非线性函数的近似计算器和使用它的地图解码器
公开(公告)号：US06922711B2
公开(公告)日：2005-07-26
申请号：US10057654
申请日：2002-01-23
申请人： Koji Kato , Takayuki Aono
发明人： Koji Kato , Takayuki Aono
IPC分类号： G06F17/17 , G06F1/035 , H03M13/45 , G06F1/02
CPC分类号： H03M13/3911 , G06F1/035 , G06F2101/10
摘要： A calculator calculates an approximate value of a function Y=log (1+e−x) using input data x. In the calculator, a decoder outputs m-bit data that represents a value corresponding to the slope of a straight line, and further outputs intercept data of the straight line. The straight line interpolates the function Y=log (1+e−x) for an interval that includes the input data x as an X-value, and has a slope of −2n. The intercept data represents Y-intercept of the straight line. A shifter shifts the input data x by |n| bits based on the m-bit data, and provides the resultant value as first term data. An adder generates the sum of the first term data and the intercept data, and outputs the generated sum as an approximate value of the function log Y=(1+e−x)
摘要翻译：计算器使用输入数据x计算函数Y = log（1 + e ^{-x ）的近似值。在计算器中，解码器输出表示与直线的斜率对应的值的m位数据，并进一步输出直线的截取数据。直线将包含输入数据x的间隔的函数Y = log（1 + e ^{-x ）内插为X值，并且具有-2 < / SUP>。截距数据表示直线的Y截距。移位器将输入数据x移位| n | 基于m位数据，并将结果值提供为第一项数据。加法器产生第一项数据和截距数据的和，并将所生成的和输出作为函数对数Y =（1 + e - O）的近似值，}}

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