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    • 5. 发明申请
    • High frequency switch circuit
    • 高频开关电路
    • US20050179506A1
    • 2005-08-18
    • US10514394
    • 2003-05-19
    • Yuji TakahashiKeiichi Numata
    • Yuji TakahashiKeiichi Numata
    • H03K17/693H03K17/06H04B1/48H01P1/10
    • H04B1/48H03K17/063H03K17/693
    • A high-frequency switch circuit has a plurality of high-frequency switches for passing and blocking a high-frequency signal between an input terminal and an output terminal depending on a control potential applied as a control signal, a high-frequency detecting terminal for detecting high-frequency signal passing through the high-frequency switch which is in ON-state, and a voltage boosting circuit for generating a potential for increasing the control potential applied to the high-frequency switch which is in ON-state in order to increase difference between the control potential applied to the high-frequency switch which is in an ON-state and the control potential applied to the high-frequency switch which is in an OFF-state, depending on an intensity or amplitude of the detected high-frequency signal.
    • 高频开关电路具有多个高频开关,用于根据作为控制信号施加的控制电位,在输入端子和输出端子之间传递和阻断高频信号,高频检测端子用于检测 高频信号通过处于导通状态的高频开关,以及升压电路,用于产生用于增加施加到处于导通状态的高频开关的控制电位的电位,以增加差分 根据检测到的高频信号的强度或幅度,施加在处于导通状态的高频开关的控制电位与施加到处于断开状态的高频开关的控制电位之间 。
    • 6. 发明授权
    • Field effect transistor logic circuit with reduced power consumption
    • 场效应晶体管逻辑电路具有降低的功耗
    • US06201416B1
    • 2001-03-13
    • US09276327
    • 1999-03-25
    • Keiichi Numata
    • Keiichi Numata
    • H03K19084
    • H03K19/0952H03K19/0013H03K19/018535
    • There is disclosed a field effect transistor logic circuit having an output terminal to be connected to a gate of an input field effect transistor in a next stage field effect transistor logic circuit. The field effect transistor logic circuit includes a depletion transistor having a drain connected to a first power supply voltage, an enhancement transistor having a drain connected at a node in common to a gate and a source of the depletion transistor. A gate of the enhancement transistor is connected to an input terminal, and a source of the enhancement transistor is connected to a second power supply voltage which is lower than the first power supply voltage. A high level potential limiting circuit is connected between the node and the output terminal, to lower a potential of the output terminal to a level which turns on a drain-source channel of the input field effect transistor of the next stage field effect transistor logic circuit but which never turns on a gate-source of the input field effect transistor of the next stage field effect transistor logic circuit, when the potential of the node is at a high level. A lower level lowering circuit having an input connected to the input terminal, is also connected between the output terminal and the second power supply voltage, for pulling down the potential of the output terminal to the potential of the second power supply voltage when the potential on the node is at a low level.
    • 公开了一种场效应晶体管逻辑电路,其具有在下一级场效应晶体管逻辑电路中连接到输入场效应晶体管的栅极的输出端。 场效应晶体管逻辑电路包括具有连接到第一电源电压的漏极的耗尽型晶体管,具有与栅极共同的节点和耗尽型晶体管的源极连接的漏极的增强型晶体管。 增强晶体管的栅极连接到输入端子,并且增强型晶体管的源极连接到低于第一电源电压的第二电源电压。 在节点和输出端子之间连接一个高电位限制电路,将输出端子的电位降低到接通下一级场效应晶体管逻辑电路的输入场效应晶体管的漏极 - 源极通道的电平 但是当节点的电位处于高电平时,它不会打开下一级场效应晶体管逻辑电路的输入场效应晶体管的栅极源。 具有连接到输入端子的输入的下降电路也连接在输出端子和第二电源电压之间,用于当电位开启时将输出端子的电位降低到第二电源电压的电位 节点处于低电平。