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1. 发明授权

US4769792A Semiconductor memory device with voltage bootstrap 失效
标题翻译：具有电压自举的半导体存储器件
公开(公告)号：US4769792A
公开(公告)日：1988-09-06
申请号：US923958
申请日：1986-10-28
申请人： Kazutaka Nogami , Takayasu Sakurai , Syuso Fujii
发明人： Kazutaka Nogami , Takayasu Sakurai , Syuso Fujii
IPC分类号： G11C5/14 , G11C7/12 , G11C8/08 , G11C11/406 , G11C11/40 , G11C13/00
CPC分类号： G11C7/12 , G11C11/406 , G11C5/145 , G11C8/08
摘要： Two or more voltage bootstrap circuits are included, and are sequentially operated. A continuous data write/read operation can be performed at a high speed. One of the two voltage bootstrap circuits is used for the data write/read operation and the other thereof is used for the refresh operation, thereby shortening the time required for refreshing.
摘要翻译：包括两个或多个电压自举电路，并且被依次操作。可以高速执行连续的数据写入/读取操作。两个电压自举电路中的一个用于数据写入/读取操作，另一个用于刷新操作，从而缩短刷新所需的时间。

2. 发明授权

US4905192A Semiconductor memory cell 失效
标题翻译：半导体存储单元
公开(公告)号：US4905192A
公开(公告)日：1990-02-27
申请号：US175252
申请日：1988-03-30
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory device includes a memory cell array, a spare memory cell array, a first addressing circuit for designating an address of the memory cell array, a second addressing circuit for designating an address of the spare memory cell array, a drive circuit for activating a select line designated by each of the first and second addressing circuits, a program circuit for generating a predetermined output based on whether the memory cell array has a defect or fault or not, and a select circuit responsive to an output from the program circuit for supplying an activation signal to the designated select line at an earlier timing when there is no fault in the memory array cell, and supplying an activation signal delayed by a time necessary for the selection of the spare memory cell array when there is a fault in the memory cell array.
摘要翻译：半导体存储器件包括存储单元阵列，备用存储单元阵列，用于指定存储单元阵列的地址的第一寻址电路，用于指定备用存储单元阵列的地址的第二寻址电路，用于激活的驱动电路由第一和第二寻址电路中的每一个指定的选择线，用于基于存储单元阵列是否具有缺陷或故障来产生预定输出的程序电路，以及响应于来自程序电路的输出的选择电路，当存储器阵列单元中没有故障时，在更早的定时向指定的选择线提供激活信号，并且当存在故障时提供延迟了选择备用存储单元阵列所需的时间的激活信号存储单元阵列。

3. 发明授权

US4984208A Dynamic read/write memory with improved refreshing operation 失效
标题翻译：动态读/写存储器，具有改进的刷新操作
公开(公告)号：US4984208A
公开(公告)日：1991-01-08
申请号：US364529
申请日：1989-06-12
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A dynamic read/write memory in which refreshing is performed within a read/write cycle so that write recovery time is not prolonged. A word line corresponding to a current address is continuously rendered operative within a write period. When a write operation is completed, the word line is rendered operative so that refreshing is initiated. A word line is rendered operative only within a given period of a read period.
摘要翻译：动态读/写存储器，其中在读/写周期内执行刷新以使写恢复时间不延长。对应于当前地址的字线在写入周期内连续地进行操作。当写入操作完成时，字线被操作，从而启动刷新。字线只能在读取周期的给定时间段内运行。

4. 发明授权

US4853897A Complementary semiconductor memory device 失效
标题翻译：互补半导体存储器件
公开(公告)号：US4853897A
公开(公告)日：1989-08-01
申请号：US128946
申请日：1987-12-04
申请人： Kazutaka Nogami , Takayasu Sakurai
发明人： Kazutaka Nogami , Takayasu Sakurai
IPC分类号： G11C11/408 , G11C11/4094 , G11C11/4099
CPC分类号： G11C11/4094 , G11C11/4085 , G11C11/4099
摘要： The invention discloses a semiconductor memory device possessing high operational reliability. In the semiconductor memory device according to the invention, a plurality of well regions of a conductivity type different from that of a semiconductor substrate are formed in the semiconductor substrate, and a memory cell array and a bit line driver are formed in other well regions, situated away from each other. With this arrangement, the number of signal lines to be connected to the well region in which the memory cell array is formed can be reduced, and the adverse influence of minority carriers generated upon operation of the bit line driver can be prevented. With this arrangement, well bias can be applied only to memory cell array. As a result, the operational reliability of the semiconductor memory device can be improved.
摘要翻译：本发明公开了具有高操作可靠性的半导体存储器件。在根据本发明的半导体存储器件中，在半导体衬底中形成不同于半导体衬底的导电类型的多个阱区，并且在其它阱区中形成存储单元阵列和位线驱动器，远离彼此。通过这种布置，可以减少要连接到其上形成存储单元阵列的阱区的信号线的数量，并且可以防止在位线驱动器的操作时产生的少数载流子的不利影响。利用这种布置，阱偏压仅可应用于存储单元阵列。结果，可以提高半导体存储器件的操作可靠性。

5. 发明授权

US4939695A Virtual type static semiconductor memory device including refresh detector circuitry 失效
标题翻译：包括刷新检测器电路的虚拟型静态半导体存储器件
公开(公告)号：US4939695A
公开(公告)日：1990-07-03
申请号：US268927
申请日：1988-11-09
申请人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Kazutaka Nogami , Hisashi Ueno
发明人： Mitsuo Isobe , Takayasu Sakurai , Kazuhiro Sawada , Kazutaka Nogami , Hisashi Ueno
IPC分类号： G11C11/403 , G11C11/406
CPC分类号： G11C11/406
摘要： A virtual type static semiconductor memory device according to the present invention comprises a refresh detector circuit for detecting the enabling operation of a refresh control circuit and a terminal for outputting to an outside a detection signal which is generated from the refresh detector circuit. The virtual type static semiconductor memory device informs a present refresh operation to the outside when it is accessed from the outside during the time period in which a refresh operation is conducted in the semiconductor memory device. A system employing the semiconductor memory device allows a slow access at that time only and allows access to be gained to the semiconductor memory device at high speed at other times.

6. 发明授权

US5459342A Field programmable gate array with spare circuit block 失效
标题翻译：具有备用电路块的现场可编程门阵列
公开(公告)号：US5459342A
公开(公告)日：1995-10-17
申请号：US146312
申请日：1993-11-02
申请人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
发明人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
IPC分类号： H01L21/82 , G06F11/20 , H01L27/118 , H03K19/173 , H01L21/70 , H01L27/00 , H03K19/177
CPC分类号： H03K19/17764
摘要： A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.
摘要翻译：现场可编程门阵列包括：多个具有逻辑电路的电路块; 至少一个具有逻辑电路的备用电路块; 一组互连，其包括至少一个互连，用于可编程地连接至少一个所述电路块和所述至少一个备用电路; 以及至少一个连接元件，其设置在所述一组互连件的互连上，其在编程时将其状态从打开状态转变为关闭状态，反之亦然。当任何一个电路块有缺陷时，由于可以用备用电路块代替有缺陷的电路块，可以通过编程连接装置来保持逻辑电路的所需功能，从而提高了现场的产量可编程门阵列，从而降低其制造成本。

7. 发明授权

US4757217A Refresh operation control circuit for semiconductor device 失效
标题翻译：半导体器件的刷新操作控制电路
公开(公告)号：US4757217A
公开(公告)日：1988-07-12
申请号：US11882
申请日：1987-02-06
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406 , H03K3/356
CPC分类号： G11C11/406
摘要： This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

8. 发明授权

US5539331A Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires 失效
标题翻译：具有传输门的现场可编程门阵列和用于编程线的连接的半导体集成电路
公开(公告)号：US5539331A
公开(公告)日：1996-07-23
申请号：US237631
申请日：1994-05-04
申请人： Fumitoshi Hatori , Kazutaka Nogami , Takayasu Sakurai , Makoto Ichida
发明人： Fumitoshi Hatori , Kazutaka Nogami , Takayasu Sakurai , Makoto Ichida
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/177 , H03K19/17704
摘要： A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.
摘要翻译：现场可编程门阵列包括：由多条第一线组成的第一线组（8）; 由多条第二线组成的第二线组（7）切换部分（9）提供了第一和第二线组（8,7）的第一和第二线之间的至少一个交点，用于在编程时确定两者之间的连接和断开; 以及响应于高栅极电压而导通的第一传输门（4）和响应于低栅极电压导通的第二传输门（5）的基站（6B），第一和第二传输门的栅极（4,5）作为公共栅极彼此连接，或者当编程的输入和输出端子和第一和第二传输门（4,5）的公共栅极时，由开关部分作为公共栅极彼此连接）分别连接到第一线组（8）的任何第一线。提供不同长度的接线用于连接现场可编程门阵列内的电路元件，第一长度的导线比第二较长长度的导线多。不同长度的电线数量根据电线长度的-2.5功率而变化。

9. 发明授权

US08618870B2 Voltage characteristic regulating method of latch circuit, voltage characteristic regulating method of semiconductor device, and voltage characteristic regulator of latch circuit 失效
标题翻译：锁存电路的电压特性调节方法，半导体器件的电压特性调节方法和锁存电路的电压特性调节器
公开(公告)号：US08618870B2
公开(公告)日：2013-12-31
申请号：US13377009
申请日：2010-06-11
申请人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
发明人： Toshiro Hiramoto , Takayasu Sakurai , Makoto Suzuki
IPC分类号： G05F1/10
CPC分类号： G11C11/413
摘要： The voltage Vdd is set to be lower than in the normal operation (step S100), then voltage is applied to each of the power-supply voltage applied node Vdd, the ground voltage applied node Vss, the semiconductor substrate and the well so that relative high voltage between the gate of turn-on transistor and the semiconductor substrate or the gate of turn-on transistor and well (steps S110 and S120). This process accomplishes rising of the threshold voltage of the transistor that is turned on, the reduction of the variation in the threshold voltage between a plurality of the transistors of the memory cell including latch circuit, and the improvement of the voltage characteristic of the memory cell.
摘要翻译：电压Vdd被设定为低于正常工作（步骤S100），然后对电源电压施加节点Vdd，接地电压施加节点Vss，半导体衬底和阱施加电压，使得相对导通晶体管的栅极与半导体衬底或导通晶体管的栅极之间的高电压（步骤S110和S120）。该处理完成导通的晶体管的阈值电压的上升，包括锁存电路的存储单元的多个晶体管之间的阈值电压的变化的减小以及存储单元的电压特性的改善。

10. 发明申请

US20060039182A1 Self-aligned row-by-row dynamic VDD SRAM 失效
标题翻译：自对准逐行动态VDD SRAM
公开(公告)号：US20060039182A1
公开(公告)日：2006-02-23
申请号：US11205466
申请日：2005-08-16
申请人： Takayasu Sakurai , Hiroshi Kawaguchi , Robert Fayez
发明人： Takayasu Sakurai , Hiroshi Kawaguchi , Robert Fayez
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A memory cell array includes a plurality of memory cells arranged in a matrix form. A word line and a power supply line respectively are connected in common to the plurality of memory cells arranged in each row. A power supply line/word line control circuit is connected to each word line and each power supply line. In accessing the plurality of memory cells row by row, the control circuit raises the voltage of the power supply line and, after the voltage of the power supply line reaches the high voltage at all the positions, starts activation of the word line. On the other hand, in turning from the access state to the non-access state, the control circuit deactivates the word line and, after the voltage of the word line changes to the ground voltage at all the positions, changes the voltage of the power supply line to the low voltage.
摘要翻译：存储单元阵列包括以矩阵形式布置的多个存储单元。字线和电源线分别连接到布置在每一行中的多个存储单元。电源线/字线控制电路连接到每个字线和每个电源线。在逐行访问多个存储单元时，控制电路提高电源线的电压，并且在所有位置的电源线的电压达到高电压之后，开始字线的激活。另一方面，在从访问状态转到非访问状态时，控制电路使字线停止，并且在字线的电压在所有位置变化为接地电压之后，改变电源的电压供电线路为低电压。

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