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1. 发明授权

US5539331A Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires 失效
标题翻译：具有传输门的现场可编程门阵列和用于编程线的连接的半导体集成电路
公开(公告)号：US5539331A
公开(公告)日：1996-07-23
申请号：US237631
申请日：1994-05-04
申请人： Fumitoshi Hatori , Kazutaka Nogami , Takayasu Sakurai , Makoto Ichida
发明人： Fumitoshi Hatori , Kazutaka Nogami , Takayasu Sakurai , Makoto Ichida
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/177 , H03K19/17704
摘要： A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.
摘要翻译：现场可编程门阵列包括：由多条第一线组成的第一线组（8）; 由多条第二线组成的第二线组（7）切换部分（9）提供了第一和第二线组（8,7）的第一和第二线之间的至少一个交点，用于在编程时确定两者之间的连接和断开; 以及响应于高栅极电压而导通的第一传输门（4）和响应于低栅极电压导通的第二传输门（5）的基站（6B），第一和第二传输门的栅极（4,5）作为公共栅极彼此连接，或者当编程的输入和输出端子和第一和第二传输门（4,5）的公共栅极时，由开关部分作为公共栅极彼此连接）分别连接到第一线组（8）的任何第一线。提供不同长度的接线用于连接现场可编程门阵列内的电路元件，第一长度的导线比第二较长长度的导线多。不同长度的电线数量根据电线长度的-2.5功率而变化。

2. 发明授权

US5459342A Field programmable gate array with spare circuit block 失效
标题翻译：具有备用电路块的现场可编程门阵列
公开(公告)号：US5459342A
公开(公告)日：1995-10-17
申请号：US146312
申请日：1993-11-02
申请人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
发明人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
IPC分类号： H01L21/82 , G06F11/20 , H01L27/118 , H03K19/173 , H01L21/70 , H01L27/00 , H03K19/177
CPC分类号： H03K19/17764
摘要： A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.
摘要翻译：现场可编程门阵列包括：多个具有逻辑电路的电路块; 至少一个具有逻辑电路的备用电路块; 一组互连，其包括至少一个互连，用于可编程地连接至少一个所述电路块和所述至少一个备用电路; 以及至少一个连接元件，其设置在所述一组互连件的互连上，其在编程时将其状态从打开状态转变为关闭状态，反之亦然。当任何一个电路块有缺陷时，由于可以用备用电路块代替有缺陷的电路块，可以通过编程连接装置来保持逻辑电路的所需功能，从而提高了现场的产量可编程门阵列，从而降低其制造成本。

3. 发明授权

US5498978A Field programmable gate array 失效
标题翻译：现场可编程门阵列
公开(公告)号：US5498978A
公开(公告)日：1996-03-12
申请号：US237851
申请日：1994-05-04
申请人： Makoto Takahashi , Fumitoshi Hatori , Kazutaka Nogami , Masanori Uchida
发明人： Makoto Takahashi , Fumitoshi Hatori , Kazutaka Nogami , Masanori Uchida
IPC分类号： H01L21/82 , G11C17/16 , H01L27/118 , H03K19/173 , H03K19/177 , H01H37/76 , H03K17/687
CPC分类号： H03K19/17796 , G11C17/16 , H03K19/17704
摘要： A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . . ) between which the programmable element to be programmed is connected and an intermediate voltage between the first and second wirings between which the programmable element not to be programmed is connected, the intermediate voltage being lower than the programming voltage to such an extent as not to affect state of the programmable elements (A11, A12, A13, . . . ).
摘要翻译：现场可编程门阵列包括：由多个第一布线（C1，C2，C3 ...）组成的第一布线组; 由多个第二布线（R1，R2，R3 ...）组成的第二布线组; 在第一布线和第二布线之间的多个交点中的至少一个布置成阵列图案的多个可编程元件（A11，A12，A13 ...），每个可编程元件连接到每个第一布线（C1，C2，C3，...）和其另一端的每个第二布线（R1，R2，R3 ...），并通过施加在第一布线以及用于将所述第一和第二布线之间的连接切换到所述两条布线之间的断开的第二布线，反之亦然; 以及用于在第一和第二布线（C1，C2，C3，...，R1，R2，R3等）之间施加编程电压的电压供应部分（CD1，RD1），其中要编程的可编程元件所述第一和第二布线之间的中间电压被连接在可编程元件不被编程之间的中间电压，所述中间电压低于编程电压至不影响可编程元件（A11，A12， A13，...）。

4. 发明授权

US5764588A Memory circuit 失效
标题翻译：存储电路
公开(公告)号：US5764588A
公开(公告)日：1998-06-09
申请号：US848223
申请日：1997-04-29
申请人： Kazutaka Nogami , Fumitoshi Hatori
发明人： Kazutaka Nogami , Fumitoshi Hatori
IPC分类号： G11C11/41 , G11C7/18 , G11C8/16 , G11C5/06
CPC分类号： G11C8/16 , G11C7/18
摘要： A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.
摘要翻译：实现具有比常规存储器件更高密度的单端口存储器或多端口存储器，同时使用相同的设计规则，通过减少每列或端口的位线数量以减少布线空间和尺寸整个记忆存储电路包括以矩阵形式布置多个存储单元的存储单元阵列，每个存储单元具有至少一个读端口; 每个连接到存储单元阵列的存储单元中的一行排列的存储单元的字线以及与存储单元阵列的存储单元中的n行（n> / = 2）对齐的存储单元连接的位线。共享n位线的存储单元的存取晶体管的电流驱动能力设定为满足1：2：的关系。。。：2n-1。这导致位线的数量和存储器的面积减少。

5. 发明授权

US07487370B2 Semiconductor device and system 有权
标题翻译：半导体器件和系统
公开(公告)号：US07487370B2
公开(公告)日：2009-02-03
申请号：US11216018
申请日：2005-09-01
申请人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
发明人： Shinichiro Shiratake , Yukihito Oowaki , Hiroyuki Hara , Tetsuya Fujita , Fumitoshi Hatori , Masataka Matsui
IPC分类号： G06F1/00
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3296 , Y02D10/172
摘要： According to the present invention, there is provided a semiconductor device including a power supply circuit which receives an external power supply voltage supplied, and outputs an internal power supply voltage not higher than the external power supply voltage; a system module which receives the internal power supply voltage, and performs a predetermined operation; and a performance monitor circuit which measures a processing speed of said system module when the internal power supply voltage is applied, and, on the basis of the processing speed, outputs a first control signal which requests to set the external power supply voltage at a first level, and a second control signal which requests said power supply circuit to set the internal power supply voltage at a second level. The power supply circuit outputs the internal power supply voltage having the second level on the basis of the second control signal applied thereto.
摘要翻译：根据本发明，提供了一种半导体器件，包括：电源电路，接收所提供的外部电源电压，并输出不高于外部电源电压的内部电源电压; 接收内部电源电压并执行预定操作的系统模块; 以及性能监视电路，其在施加所述内部电源电压时测量所述系统模块的处理速度，并且基于所述处理速度，输出请求将所述外部电源电压设置为第一的第一控制信号电平和第二控制信号，其请求所述电源电路将内部电源电压设定在第二电平。电源电路基于施加到其上的第二控制信号输出具有第二电平的内部电源电压。

6. 发明申请

US20060061401A1 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US20060061401A1
公开(公告)日：2006-03-23
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

7. 发明授权

US08395410B2 Semiconductor integrated circuit and system of controlling the same 失效
标题翻译：半导体集成电路及其控制系统
公开(公告)号：US08395410B2
公开(公告)日：2013-03-12
申请号：US13036349
申请日：2011-02-28
申请人： Fumitoshi Hatori
发明人： Fumitoshi Hatori
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/0016
摘要： According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, and a signal propagation control circuit. The first circuit is configured to have a first power supply terminal. The second circuit is configured to have a second power supply terminal independent of the first power supply terminal. The signal propagation control circuit is configured to provide a first fixed value to the second circuit for a predetermined period after power is supplied to the second circuit, and after the predetermined period, configured to control whether to transfer an output signal from the first circuit to the second circuit or provide the first fixed value to the second circuit.
摘要翻译：根据一个实施例，半导体集成电路包括第一电路，第二电路和信号传播控制电路。第一电路被配置为具有第一电源端子。第二电路被配置为具有独立于第一电源端子的第二电源端子。信号传播控制电路被配置为在向第二电路供电之后的预定时间段内向第二电路提供第一固定值，并且在预定时段之后，被配置为控制是否将来自第一电路的输出信号传送到第二电路或将第一固定值提供给第二电路。

8. 发明申请

US20120062314A1 SEMICONDUCTOR INTEGRATED CIRCUIT AND SYSTEM OF CONTROLLING THE SAME 失效
标题翻译：半导体集成电路及其控制系统
公开(公告)号：US20120062314A1
公开(公告)日：2012-03-15
申请号：US13036349
申请日：2011-02-28
申请人： Fumitoshi Hatori
发明人： Fumitoshi Hatori
IPC分类号： H01L25/00
CPC分类号： H03K19/0016
摘要： According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, and a signal propagation control circuit. The first circuit is configured to have a first power supply terminal. The second circuit is configured to have a second power supply terminal independent of the first power supply terminal. The signal propagation control circuit is configured to provide a first fixed value to the second circuit for a predetermined period after power is supplied to the second circuit, and after the predetermined period, configured to control whether to transfer an output signal from the first circuit to the second circuit or provide the first fixed value to the second circuit.
摘要翻译：根据一个实施例，半导体集成电路包括第一电路，第二电路和信号传播控制电路。第一电路被配置为具有第一电源端子。第二电路被配置为具有独立于第一电源端子的第二电源端子。信号传播控制电路被配置为在向第二电路供电之后的预定时间段内向第二电路提供第一固定值，并且在预定时段之后，被配置为控制是否将来自第一电路的输出信号传送到第二电路或将第一固定值提供给第二电路。

9. 发明授权

US06546048B1 Pulse width modulation waveform generating circuit 失效
标题翻译：脉宽调制波形发生电路
公开(公告)号：US06546048B1
公开(公告)日：2003-04-08
申请号：US09372720
申请日：1999-08-11
申请人： Fuyuki Ichiba , Kojiro Suzuki , Fumitoshi Hatori
发明人： Fuyuki Ichiba , Kojiro Suzuki , Fumitoshi Hatori
IPC分类号： H03K708
CPC分类号： H03K7/08 , H02M3/157 , H03K5/133
摘要： An object of the present invention to provide a pulse width modulation waveform generating circuit that it is possible to reduce circuit size and power consumption. A pulse width modulation waveform generating circuit comprises a ring oscillator having 64 pieces of inverters connected in series, inverters connected to output terminals of odd numbered stages of inverters in the ring oscillator, a multiplexer, a change detecting circuit, and an RS flip-flop. The multiplexer is supplied with output signals of even numbered stages of the inverters in the ring oscillator and output signal of the inverter. One of their signals is selected in accordance with logic of a digital signal. The RS flip-flop is set at time an edge detecting pulse is outputted from the change detecting circuit, and is reset at time an edge detecting pulse is outputted from the change detecting circuit.
摘要翻译：本发明的目的是提供一种可以减小电路尺寸和功耗的脉宽调制波形发生电路。脉宽调制波形发生电路包括一个环形振荡器，它具有串联连接的64个反相器，反相器连接到环形振荡器中奇数级反相器的输出端，多路复用器，变化检测电路和RS触发器。多路复用器提供环形振荡器中的反相器偶数级的输出信号和反相器的输出信号。根据数字信号的逻辑选择它们中的一个信号。在从变化检测电路输出边缘检测脉冲的时刻设定RS触发器，并且在从变化检测电路输出边缘检测脉冲的时刻被复位。

10. 发明授权

US07236035B2 Semiconductor device adapted to minimize clock skew 有权
标题翻译：半导体器件适合于最小化时钟偏移
公开(公告)号：US07236035B2
公开(公告)日：2007-06-26
申请号：US10990537
申请日：2004-11-18
申请人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
发明人： Shinichiro Shiratake , Yukihito Oowaki , Fumitoshi Hatori , Mototsugu Hamada , Hiroyuki Hara
IPC分类号： G06F1/04
CPC分类号： G06F1/10
摘要： A first logic circuit has its supply voltage controlled. A second logic circuit operates in response to an external clock signal. An adjustment circuit includes a first delay circuit supplied with the external clock signal, and a detection circuit which detects a skew between timing of a first clock signal output from the first logic circuit and a second clock signal output from the second logic circuit section. The adjustment circuit adjusts the delay time of the first delay circuit according to the result of the detection by the detection circuit and applies an output signal of the first delay circuit to the first logic circuit as a third clock signal.
摘要翻译：第一个逻辑电路的电源电压被控制。第二逻辑电路响应于外部时钟信号而工作。调整电路包括提供有外部时钟信号的第一延迟电路和检测电路，其检测从第一逻辑电路输出的第一时钟信号的定时与从第二逻辑电路部分输出的第二时钟信号之间的偏差。调整电路根据检测电路的检测结果来调整第一延迟电路的延迟时间，并将第一延迟电路的输出信号作为第三时钟信号施加到第一逻辑电路。

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