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1. 发明申请

US20140043063A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140043063A1
公开(公告)日：2014-02-13
申请号：US14112926
申请日：2012-03-26
申请人： Kazuo Tomita , Toshiyuki Oashi , Hidenori Sato
发明人： Kazuo Tomita , Toshiyuki Oashi , Hidenori Sato
IPC分类号： H01L23/52
CPC分类号： H01L29/0696 , H01L21/823871 , H01L23/52 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L29/1095 , H01L29/45 , H01L2924/0002 , H01L2924/00
摘要： A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection.
摘要翻译：栅极互连部分包括第一栅极互连部分，第二栅极互连部分和第三栅极互连部分。第一栅极互连部分形成为平行于Y轴方向朝向电源互连并延伸到元件形成区域内的规定位置。第二栅极互连部分形成为平行于从第一栅极互连部分朝向电源互连方向相对于Y轴方向倾斜弯曲的方向，并延伸穿过元件形成区域和元件隔离绝缘膜之间的边界，它与X轴方向平行。第三栅极互连部分还从第二栅极互连部分向电源互连方向平行于Y轴方向延伸。

2. 发明授权

US09054103B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US09054103B2
公开(公告)日：2015-06-09
申请号：US14112926
申请日：2012-03-26
申请人： Kazuo Tomita , Toshiyuki Oashi , Hidenori Sato
发明人： Kazuo Tomita , Toshiyuki Oashi , Hidenori Sato
IPC分类号： H01L23/52 , H01L27/02 , H01L21/8238
CPC分类号： H01L29/0696 , H01L21/823871 , H01L23/52 , H01L23/5286 , H01L27/0207 , H01L27/092 , H01L29/1095 , H01L29/45 , H01L2924/0002 , H01L2924/00
摘要： A gate interconnection portion includes a first gate interconnection portion, a second gate interconnection portion, and a third gate interconnection portion. The first gate interconnection portion is formed in parallel to a Y axis direction toward a power supply interconnection and extends to a prescribed position within an element formation region. The second gate interconnection portion is formed in parallel to a direction obliquely bent with respect to the Y-axis direction from the first gate interconnection portion toward the power supply interconnection, and extends across a boundary between the element formation region and an element isolation insulating film, which is in parallel to an X axis direction. The third gate interconnection portion further extends in parallel to the Y-axis direction from the second gate interconnection portion toward the power supply interconnection.
摘要翻译：栅极互连部分包括第一栅极互连部分，第二栅极互连部分和第三栅极互连部分。第一栅极互连部分形成为平行于Y轴方向朝向电源互连并延伸到元件形成区域内的规定位置。第二栅极互连部分形成为平行于从第一栅极互连部分朝向电源互连方向相对于Y轴方向倾斜弯曲的方向，并延伸穿过元件形成区域和元件隔离绝缘膜之间的边界，它与X轴方向平行。第三栅极互连部分还从第二栅极互连部分向电源互连方向平行于Y轴方向延伸。

3. 发明授权

US09036896B2 Inspection system and method for inspecting line width and/or positional errors of a pattern 有权
标题翻译：用于检查图案的线宽和/或位置误差的检查系统和方法
公开(公告)号：US09036896B2
公开(公告)日：2015-05-19
申请号：US13083157
申请日：2011-04-08
申请人： Takanao Touya , Shuichi Tamamushi , Hidenori Sato , Hiroyuki Tanizaki , Takeshi Fujiwara , Eiji Sawa , Kentaro Okuda , Hiroyuki Ikeda , Hiromu Inoue , Hiroshi Tsukada
发明人： Takanao Touya , Shuichi Tamamushi , Hidenori Sato , Hiroyuki Tanizaki , Takeshi Fujiwara , Eiji Sawa , Kentaro Okuda , Hiroyuki Ikeda , Hiromu Inoue , Hiroshi Tsukada
IPC分类号： G06K9/00 , G06T7/00
CPC分类号： G06T7/001 , G01N21/9501 , G01N21/9503 , G01N21/956 , G06T7/0004 , G06T7/0006 , G06T7/70 , G06T7/74 , G06T2207/10004 , G06T2207/30141 , G06T2207/30148
摘要： A method and system for imaging an object to be inspected and obtaining an optical image; creating a reference image from design pattern data; preparing an inspection recipe including one or more templates and parameter settings necessary for the inspection; checking the pattern and the template against each other, and selecting the reference image which corresponds to the template; detecting first and second edges in the selected reference image in accordance with the parameter setting using determined coordinates as a reference; detecting first and second edges in the optical image, this optical image corresponds to the selected reference image; and determining an inspection value by acquiring the difference between the line width of the optical image and the reference image using the first edge and second edge of the reference image and the first edge and second edges of the optical image.
摘要翻译：一种用于对待检查对象进行成像并获得光学图像的方法和系统; 从设计模式数据创建参考图像; 准备包括一个或多个模板和检查所需的参数设置的检查配方; 检查图案和模板，并选择与模板对应的参考图像; 根据使用确定的坐标作为参考的参数设置来检测所选参考图像中的第一和第二边缘; 检测光学图像中的第一和第二边缘，该光学图像对应于所选择的参考图像; 以及通过使用参考图像的第一边缘和第二边缘以及光学图像的第一边缘和第二边缘获取光学图像的线宽和参考图像之间的差来确定检查值。

4. 发明授权

US08354730B2 Manufacturing method of semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08354730B2
公开(公告)日：2013-01-15
申请号：US11997436
申请日：2006-08-25
申请人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
发明人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/2007 , H01L21/76232 , H01L21/8221 , H01L23/481 , H01L24/94 , H01L2224/2518 , H01L2924/01004 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
摘要翻译：提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面分离基板和分离穿透电极的穿透分离部分。因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。因此，可以提高具有三维结构的半导体器件的元件特性。

5. 发明授权

US07320527B2 Mirror and angle detection device 失效
标题翻译：镜面和角度检测装置
公开(公告)号：US07320527B2
公开(公告)日：2008-01-22
申请号：US11235211
申请日：2005-09-27
申请人： Ayako Yamada , Hidenori Sato
发明人： Ayako Yamada , Hidenori Sato
IPC分类号： G02B7/182 , G60R1/06
CPC分类号： B60R1/072
摘要： A vehicle mirror comprises: a mirror surface; an actuator 100 which tilts the mirror surface; a plate pivot 110, which changes its direction together with the mirror surface; a spring 112, which applies a resilient force to the plate pivot 110 in the direction substantially vertical to the mirror surface; a guide spring 114 which is fitted to the end of the spring 112 at the side far from the interlocking member; a semiconductor pressure sensor 116, which is in contact with the guide spring at substantially one point so as to detect a load loaded on the one point from the pressing member; and a signal outputting portion which outputs a signal depending upon the tilted angle of the mirror surface based on the force detected by the semiconductor pressure sensor 116.
摘要翻译：车辆镜子包括：镜面; 致动器100，其使镜面倾斜; 平板枢轴110，其与镜面一起改变其方向; 弹簧112，其在基本上垂直于镜面的方向上向板枢轴110施加弹性力; 导向弹簧114，其在远离联锁构件的一侧装配到弹簧112的端部; 半导体压力传感器116，其基本上一点与导向弹簧接触，以便检测从按压部件加载到该一个点上的负载; 以及信号输出部，其基于由半导体压力传感器116检测出的力，输出取决于镜面的倾斜角度的信号。

6. 发明授权

US07208391B2 Method of manufacturing a semiconductor integrated circuit device that includes forming an isolation trench around active regions and filling the trench with two insulating films 有权
标题翻译：制造半导体集成电路器件的方法包括在有源区周围形成隔离沟槽并用两个绝缘膜填充沟槽
公开(公告)号：US07208391B2
公开(公告)日：2007-04-24
申请号：US11149538
申请日：2005-06-10
申请人： Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
发明人： Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
IPC分类号： H01L21/762
CPC分类号： H01L21/76229 , H01L21/02271 , H01L21/02282 , H01L21/3125 , H01L21/31612 , H01L27/0211 , H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10844 , H01L27/10894
摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.
摘要翻译：一种制造半导体集成电路器件的方法包括以下步骤：在半导体衬底的隔离区域中形成隔离沟槽，通过涂覆方法沉积的第一绝缘膜将隔离沟填充到其深度方向上的预定中间位置，用第二绝缘膜填充绝缘沟槽的剩余深度部分，然后在半导体衬底上形成多个图案，在多个图案之间填充形成沟槽直到预定中间位置的沟槽沟槽深度方向与通过涂覆方法沉积的第三绝缘膜，并且填充第三绝缘膜填充有比第三绝缘膜更难蚀刻的第四绝缘膜的沟槽的剩余部分。该方法还可以包括在第一绝缘膜沉积之前在具有相对不同的平面尺寸的隔离区的相对大的隔离区域中形成伪图案的步骤。

7. 发明申请

US20050239257A1 Method of manufacturing a semiconductor integrated circuit device and a semiconductor integrated circuit device 有权
公开(公告)号：US20050239257A1
公开(公告)日：2005-10-27
申请号：US11149538
申请日：2005-06-10
申请人： Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
发明人： Hidenori Sato , Norio Suzuki , Akira Takamatsu , Hiroyuki Maruyama , Takeshi Saikawa , Katsuhiko Hotta , Hiroyuki Ichizoe
IPC分类号： H01L21/76 , G02B17/00 , G02B21/00 , G02B23/00 , H01L21/302 , H01L21/312 , H01L21/316 , H01L21/461 , H01L21/762 , H01L21/8239 , H01L21/8242 , H01L27/02 , H01L27/10 , H01L27/105 , H01L27/108
CPC分类号： H01L21/76229 , H01L21/02271 , H01L21/02282 , H01L21/3125 , H01L21/31612 , H01L27/0211 , H01L27/105 , H01L27/1052 , H01L27/10814 , H01L27/10844 , H01L27/10894
摘要： A method for manufacturing a semiconductor integrated circuit device includes the steps of forming an isolation trench in an isolation region of a semiconductor substrate, filling the isolation trench up to predetermined middle position in its depth direction with a first insulating film deposited by a coating method, filling a remaining depth portion of the isolation trench into which the first insulating film is filled with a second insulating film, then forming a plurality of patterns on the semiconductor substrate, filling a trench forming between the plurality of patterns up to predetermined middle position in a trench depth direction with a third insulating film deposited by a coating method, and filling a remaining portion of the trench into which the third insulating film is filled with a fourth insulating film that is more difficult to etch than the third insulating film. The method may also include the step of forming dummy patters in a relatively large isolation region of isolation regions with relatively different planar dimensions before the first insulating film is deposited.

8. 发明授权

US06905982B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US06905982B2
公开(公告)日：2005-06-14
申请号：US10477539
申请日：2002-04-19
申请人： Hidenori Sato , Katsuhiko Ichinose , Yukino Ishii , Tomoko Jinbo
发明人： Hidenori Sato , Katsuhiko Ichinose , Yukino Ishii , Tomoko Jinbo
IPC分类号： H01L21/8247 , C23C16/34 , C23C16/452 , H01L21/28 , H01L21/318 , H01L21/60 , H01L21/8238 , H01L21/8239 , H01L21/8242 , H01L27/092 , H01L27/10 , H01L27/108 , H01L27/115 , H01L29/51 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/31
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/452 , H01L21/02271 , H01L21/02274 , H01L21/28194 , H01L21/3185 , H01L21/76897 , H01L27/1052 , H01L27/10888 , H01L27/10894 , H01L29/518 , H01L2924/0002 , H01L2924/00
摘要： A CVD device (100) used for depositing a silicon nitride has a structure in which a hot wall furnace (103) for thermally degrading a source gas and a chamber (101) for forming a film over a surface of a wafer (1) are separated from each other. The hot wall furnace (103) for thermally degrading the source gas is provided above the chamber (101), and a heater (104) capable of setting the inside of the furnace at a high temperature atmosphere of approximately 1200° C. is provided at the outer periphery thereof. The source gas, supplied to the hot wall furnace (103) through pipes (105) and (106), is thermally degraded in this furnace in advance, and degraded components thereof are supplied on a stage (102) of the chamber (101) to form a film on the surface of the wafer (1).
摘要翻译：用于沉积氮化硅的CVD装置（100）具有如下结构：在晶片（1）的表面上用于使源气体热降解的热壁炉（103）和用于形成膜的室（101）彼此分离。用于使源气体热降解的热壁炉（103）设置在室（101）的上方，并且能够在大约1200℃的高温气氛下将炉内部设置的加热器（104）设置在其外围。通过管道（105）和（106）供应到热壁炉（103）的源气体预先在该炉中热劣化，并且将其劣化的组分供应到室（101）的台（102）上，以在晶片（1）的表面上形成膜。

9. 发明授权

US06632750B2 Manufacturing method of semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US06632750B2
公开(公告)日：2003-10-14
申请号：US09905887
申请日：2001-07-17
申请人： Hidenori Sato , Yoshiyuki Hayashi , Toshio Ando
发明人： Hidenori Sato , Yoshiyuki Hayashi , Toshio Ando
IPC分类号： H01L2131
CPC分类号： H01L21/0217 , C23C16/345 , H01L21/02271 , H01L21/02304 , H01L21/3185 , H01L27/11 , H01L27/1104
摘要： Described is a manufacturing method of a semiconductor integrated circuit device by depositing a silicon nitride film to give a uniform thickness over the main surface of a semiconductor wafer having a high pattern density region and a low pattern density region. This is attained by, upon depositing a silicon nitride film over a substrate having a high gate-electrode-pattern density region and a low gate-electrode-pattern density region by using a single-wafer cold-wall thermal CVD reactor, setting a flow rate ratio of ammonia (NH3) to monosilane (SiH4) greater than that upon deposition of a silicon nitride film over a flat substrate.
摘要翻译：描述了通过在具有高图案密度区域和低图案密度区域的半导体晶片的主表面上沉积氮化硅膜以获得均匀厚度的半导体集成电路器件的制造方法。这是通过使用单晶片冷壁热CVD反应器在具有高栅电极图案密度区域和低栅电极图案密度区域的衬底上沉积氮化硅膜来实现的，氨氮（NH 3 ）与单硅烷（SiH 4 PDAT>）的速率比大于沉积氮化硅膜时在平坦的基底上

10. 发明授权

US06607964B2 Method of manufacturing semiconductor device 失效
公开(公告)号：US06607964B2
公开(公告)日：2003-08-19
申请号：US09874110
申请日：2001-06-06
申请人： Hidenori Sato , Shinya Soeda
发明人： Hidenori Sato , Shinya Soeda
IPC分类号： H01L2120
CPC分类号： H01L27/10894 , H01L21/28518 , H01L21/823418 , H01L21/823468 , H01L27/10873
摘要： A first silicide protection film is deposited on a silicon substrate, a first resist pattern having an opening at a prescribed position is formed, a portion of the first silicide protection film exposed from the opening of the first resist pattern is removed to form a first opening in the first silicide protection film, an N+ diffusion layer is formed in a portion of the silicon substrate exposed from the first opening, the first resist pattern is removed, and a metallic film is deposited to form a first silicide layer on the N+ diffusion layer according to a silicide process. Thereafter, a second silicide protection film is deposited, a second resist pattern having an opening at a prescribed position is formed, portions of the first and second silicide protection films exposed from the opening of the second resist pattern are removed to form a second opening in the first and second silicide protection films, a P+ diffusion layer is formed in a portion of the silicon substrate exposed from the second opening, the second resist pattern is removed, and a metallic film is deposited to form a second silicide layer on the P+ diffusion layer according to the silicide process. Therefore, silicide layers having characteristics optimum to the diffusion layers can be formed, and the number of mask matching operations can be reduced.

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