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1. 发明授权

US08354730B2 Manufacturing method of semiconductor device and semiconductor device 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US08354730B2
公开(公告)日：2013-01-15
申请号：US11997436
申请日：2006-08-25
申请人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
发明人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
IPC分类号： H01L21/70
CPC分类号： H01L21/76898 , H01L21/2007 , H01L21/76232 , H01L21/8221 , H01L23/481 , H01L24/94 , H01L2224/2518 , H01L2924/01004 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS•FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
摘要翻译：提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面分离基板和分离穿透电极的穿透分离部分。因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。因此，可以提高具有三维结构的半导体器件的元件特性。

2. 发明申请

US20100090307A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件和半导体器件的制造方法
公开(公告)号：US20100090307A1
公开(公告)日：2010-04-15
申请号：US11997436
申请日：2006-08-25
申请人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
发明人： Satoshi Moriya , Toshio Saito , Goichi Yokoyama , Tsuyoshi Fujiwara , Hidenori Sato , Nobuaki Miyakawa
IPC分类号： H01L29/06 , H01L21/76
CPC分类号： H01L21/76898 , H01L21/2007 , H01L21/76232 , H01L21/8221 , H01L23/481 , H01L24/94 , H01L2224/2518 , H01L2924/01004 , H01L2924/04941 , H01L2924/1305 , H01L2924/14 , H01L2924/00
摘要： A structure obtaining a desired integrated circuit by sticking together a plurality of semiconductor substrates and electrically connecting integrated circuits formed on semiconductor chips of the respective semiconductor substrates is provided, and a penetrating electrode penetrating between a main surface and a rear surface of each of the semiconductor substrates and a penetrating separation portion separating the penetrating electrode are separately arranged. Thereby, after forming an insulation trench portion for formation of the penetrating separation portion on the semiconductor substrate, a MIS·FET is formed, and then, a conductive trench portion for formation of the penetrating electrode can be formed. Therefore, element characteristics of a semiconductor device having a three-dimensional structure can be improved.
摘要翻译：提供了通过将形成在各个半导体衬底的半导体芯片上的多个半导体衬底和电连接集成电路粘合在一起而获得所需集成电路的结构，并且穿透电极穿透每个半导体衬底的主表面和后表面分离基板和分离穿透电极的穿透分离部分。因此，在半导体衬底上形成用于形成穿透分离部分的绝缘沟槽部分之后，形成MIS·FET，然后形成用于形成穿透电极的导电沟槽部分。因此，可以提高具有三维结构的半导体器件的元件特性。

3. 发明授权

US07948088B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US07948088B2
公开(公告)日：2011-05-24
申请号：US12063606
申请日：2006-08-25
申请人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
发明人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L21/763 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/50 , H01L27/0203 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
摘要翻译：为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生导致膜或翘曲和晶片（W2）的裂纹被阻止。

4. 发明申请

US20090174080A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20090174080A1
公开(公告)日：2009-07-09
申请号：US12063606
申请日：2006-08-25
申请人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
发明人： Toshio Saito , Satoshi Moriya , Morio Nakamura , Goichi Yokoyama , Tatsuyuki Saito , Nobuaki Miyakawa
IPC分类号： H01L23/522
CPC分类号： H01L25/0657 , H01L21/763 , H01L21/76898 , H01L21/823871 , H01L21/823878 , H01L23/3128 , H01L23/481 , H01L24/45 , H01L24/48 , H01L25/50 , H01L27/0203 , H01L2224/45144 , H01L2224/48227 , H01L2224/48465 , H01L2225/0651 , H01L2225/06513 , H01L2924/00014 , H01L2924/01029 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/13091 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： In order to improve the manufacturing yield of a semiconductor device having a three-dimensional structure in which a plurality of chips are stacked and attached to each other, the opening shape of each of conductive grooves (4A) formed in each chip (C2) obtained from a wafer (W2) is rectangular, and the number of the conductive grooves (4A) whose long-sides are directed in a Y direction and the number of the conductive grooves (4A) whose long-sides are directed in an X direction perpendicular to the Y direction are made to be approximately equal to each other number in the entire wafer (W2), whereby the film stress upon embedding of a conductive film into the interior of the conductive grooves is reduced, and generation of exfoliation and micro-cracks in the conductive film or warpage and cracks of the wafer (W2) are prevented.
摘要翻译：为了提高具有多个芯片彼此堆叠并附接的三维结构的半导体器件的制造成品，形成在每个芯片（C2）中的每个导电槽（4A）的开口形状获得从晶片（W2）的长方形的长方形的导体槽（4A）的长度方向的长度方向的数量和长边方向的X方向的导体槽的数量使整个晶片（W2）的Y方向大致相等，由此导电膜嵌入导电槽内的膜应力减小，剥离和微裂纹的产生导致膜或翘曲和晶片（W2）的裂纹被阻止。

5. 发明授权

US07795137B2 Manufacturing method of semiconductor device 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US07795137B2
公开(公告)日：2010-09-14
申请号：US12063718
申请日：2006-08-25
申请人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
发明人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
IPC分类号： H01L21/4763
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/823871 , H01L23/481 , H01L23/585 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/0694 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.
摘要翻译：当将钨膜（43）嵌入形成在晶片（W2）和氧化硅膜（36）上的导电槽（4A）内并具有高纵横比，钨膜的成膜和回蚀（ 43）在相同装置的腔室中连续地进行，因此，在一个成膜步骤中沉积的钨膜（43）的膜厚变薄。由此，避免了钨膜（43）的剥离，微裂纹的产生，以及晶片（W2）的翘曲和裂纹的发生等问题。

6. 发明申请

US20100015797A1 MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的制造方法
公开(公告)号：US20100015797A1
公开(公告)日：2010-01-21
申请号：US12063718
申请日：2006-08-25
申请人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
发明人： Toshio Saito , Akira Otaguro , Manabu Otake , Yoshiya Takahira , Namio Katagiri , Nobuaki Miyakawa
IPC分类号： H01L21/768
CPC分类号： H01L25/50 , H01L21/76898 , H01L21/823871 , H01L23/481 , H01L23/585 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L27/0694 , H01L2224/32145 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/73265 , H01L2225/06513 , H01L2225/06541 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/10253 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/00 , H01L2224/05599 , H01L2924/00012
摘要： When a tungsten film (43) is embedded inside of a conductive groove (4A) formed in a wafer (W2) and a silicon oxide film (36) thereon and having a high aspect ratio, film formation and etch back of the tungsten film (43) are successively performed in a chamber of the same apparatus, therefore, a film thickness of the tungsten film (43) deposited in one film formation step is made to be thin. Whereby problems, such as exfoliation of the tungsten film (43), generation of micro-cracks, and occurrence of warpage and cracks of the wafer (W2), are avoided.
摘要翻译：当将钨膜（43）嵌入形成在晶片（W2）和氧化硅膜（36）上的导电槽（4A）内并具有高纵横比，钨膜的成膜和回蚀（ 43）在相同装置的腔室中连续地进行，因此，在一个成膜步骤中沉积的钨膜（43）的膜厚变薄。由此，避免了钨膜（43）的剥离，微裂纹的产生，以及晶片（W2）的翘曲和裂纹的发生等问题。

7. 发明授权

US07569476B2 Semiconductor integrated circuit device and a method of manufacturing the same 有权
标题翻译：半导体集成电路器件及其制造方法
公开(公告)号：US07569476B2
公开(公告)日：2009-08-04
申请号：US11444316
申请日：2006-06-01
申请人： Kensuke Ishikawa , Tatsuyuki Saito , Masanori Miyauchi , Toshio Saito , Hiroshi Ashihara
发明人： Kensuke Ishikawa , Tatsuyuki Saito , Masanori Miyauchi , Toshio Saito , Hiroshi Ashihara
IPC分类号： H01L21/4763
CPC分类号： H01L21/2855 , H01L21/76807 , H01L21/76838 , H01L21/76843 , H01L21/76864 , H01L21/76873 , H01L23/5226 , H01L23/5283 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： In manufacturing a semiconductor integrated circuit device, an interconnect trench and a contact hole are formed in an interlayer insulating film formed over a first-level interconnect on a semiconductor substrate, a barrier film is formed inside of the trench and contact hole so that its film thickness increases from the center of the bottom of the hole toward the sidewalls all around the bottom of the contact hole, a copper film is formed over the barrier film, and a second-level interconnect and a connector portion (plug) are formed by polishing by CMP. In this way, the geometrically shortest pathway of an electrical current flowing from the second-level interconnect toward the first-level interconnect through a connector portion (plug) does not coincide with a thin barrier film portion which has the lowest electrical resistance, so that the current pathway can be dispersed and a concentration of electrons does not occur readily.
摘要翻译：在制造半导体集成电路器件时，在形成于半导体衬底上的第一级互连件上的层间绝缘膜中形成互连沟槽和接触孔，在沟槽和接触孔内部形成阻挡膜，使其膜厚度从孔的底部的中心朝向接触孔底部的侧壁增加，在阻挡膜上形成铜膜，并且通过抛光形成第二级互连和连接器部分（插塞）通过CMP。以这种方式，通过连接器部分（插头）从第二级互连件流向第一级互连件的电流的几何最短路径与具有最低电阻的薄阻挡膜部分不一致，使得电流路径可以分散，并且电子的浓度不容易发生。

8. 发明申请

US20060013101A1 Audio apparatus and its reproduction program 失效
标题翻译：音频设备及其再现程序
公开(公告)号：US20060013101A1
公开(公告)日：2006-01-19
申请号：US10514277
申请日：2002-09-10
申请人： Kazuhiro Kawana , Toshio Saito , Hareo Hamada , Noriyuki Hanawa
发明人： Kazuhiro Kawana , Toshio Saito , Hareo Hamada , Noriyuki Hanawa
IPC分类号： G11B3/74
CPC分类号： H04S5/005 , H04S3/00
摘要： The input signal X of one channel is divided by a multi-stage delay processing device Z−1 and each of the outputs is superimposed by a specified coefficient by a coefficient processing device W0, W1, . . . , Wk. The results are added by an adder , thereby providing a correlation eliminating filter for extracting a signal component from the input signal X of one channel having a high correlation with the input signal Y of the other channel. There is provided a coefficient updating processing device 5 for successively changing the feature of the correlation eliminating filter according to an error signal e obtained from the output signal RES and the input signal Y from the other channel, and the input signal X of one channel. A surround signal is obtained from a difference between the output RES from the correlation eliminating filter and the input signal Y of the othe channel. Thus, upon reproduction of a two channels stereo signal, it is possible to generate a surround signal not giving uncomfortable feeling to a listener.
摘要翻译：一个通道的输入信号X由多级延迟处理装置Z0-1分频，并且每个输出由系数处理装置W 0 叠加指定的系数， SUB，W 1，...，。。，W k k。结果由加法器添加，从而提供一个相关消除滤波器，用于从与另一个信道的输入信号Y具有高相关性的一个信道的输入信号X中提取信号分量。提供了一种系数更新处理装置5，用于根据从另一个信道得到的输出信号RES和输入信号Y以及一个信道的输入信号X依次改变相关消除滤波器的特征。从相关消除滤波器的输出RES和通道的输入信号Y之间的差获得环绕信号。因此，在再现双声道立体声信号时，可以产生不给收听者带来不适感的环绕信号。

9. 发明申请

US20050174896A1 Dynamic vibration absorber, optical disk apparatus, and method for determining corresponding vibration frequency of dynamic vibration absorber 失效
标题翻译：动态吸振器，光盘装置及动态吸振器相应振动频率的确定方法
公开(公告)号：US20050174896A1
公开(公告)日：2005-08-11
申请号：US10519795
申请日：2003-11-21
申请人： Toshio Saito , Hiroshi Ohyama
发明人： Toshio Saito , Hiroshi Ohyama
IPC分类号： F16F15/02 , G11B25/04 , G11B33/08 , G11B7/085
CPC分类号： G11B33/08
摘要： A disk device (10) comprises a case (11) for supporting the entire disk device (10), a base chassis (12) on which a spindle motor (21) for rotating the disk is set, a counterweight (13) for absorbing vibration of the base chassis (12), and a plurality of elastic bodies (14a-14d) for mutually supporting the case (11), the base chassis (12) and the counterweight (13). The case (11), the base chassis (12), and the counterweight (13) are supported by the common elastic bodies (14a-14d). As a result, there can be provided the dynamic vibration absorber in which the number of parts is not increased and a cost can be reduced, and the optical disk device (10) using the dynamic vibration absorber.
摘要翻译：磁盘装置（10）包括用于支撑整个磁盘装置（10）的壳体（11），设置用于旋转磁盘的主轴电动机（21）的底架（12），用于吸收底架（12）的振动，以及用于相互支撑壳体（11），底架（12）和配重（13）的多个弹性体（14a-14d）。壳体（11），底架（12）和配重（13）由共同的弹性体（14a-14d）支撑。其结果是，能够提供不增加部件数量并且可以降低成本的动态吸振器，以及使用动态吸振体的光盘装置（10）。

10. 发明授权

US06676401B2 In-mold gate opening and closing mechanism and metal mold for injection molding 失效
标题翻译：模内门开闭机构和注塑成型用金属模具
公开(公告)号：US06676401B2
公开(公告)日：2004-01-13
申请号：US10023991
申请日：2001-12-21
申请人： Toshio Saito , Makoto Ohno
发明人： Toshio Saito , Makoto Ohno
IPC分类号： B29C4523
CPC分类号： B29C45/28
摘要： The present invention relates to an in-mold gate opening and closing mechanism in which it is easy to adjust the gate balance, more specially, in an in-mold gate opening and closing mechanism, in which a gate pin disposed in a gate in a mold is moved in line with resin pressure in the gate, the gate is opened by the gate pin escaping from the gate when the resin pressure exceeds an appointed pressure level when filling resin, and the gate is closed by the gate pin moving the gate direction when the resin pressure is lowered from the appointed pressure level when a filling of the resin is completed, wherein the gate is opened by a gate pin escaping from the gate when the resin pressure exceeds a pressing force of a spring adjusted by a mechanism for adjusting the spring pressure when filling resin.
摘要翻译：本发明涉及一种在模内门打开和关闭机构中，其中容易地调整门平衡，更具体地说，在模内门打开和关闭机构中，其中设置在门内的门极模具与浇口中的树脂压力一致地移动，当树脂压力超过规定的压力水平时，浇注浇口从闸门开口打开门，并且门被门闸关闭当树脂压力在树脂填充完成时从规定的压力水平降低时，当树脂压力超过由用于调节的机构调节的弹簧的按压力时，门从闸门排出的门被打开填充树脂时的弹簧压力。

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