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1. 发明申请

US20100301411A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100301411A1
公开(公告)日：2010-12-02
申请号：US12787052
申请日：2010-05-25
申请人： Yasuhiro TAKEDA , Kazunori Fujita , Haruki Yoneda
发明人： Yasuhiro TAKEDA , Kazunori Fujita , Haruki Yoneda
IPC分类号： H01L29/78
CPC分类号： H01L29/7816 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/42368 , H01L29/66681 , H01L29/7823
摘要： The invention prevents a source-drain breakdown voltage of a DMOS transistor from decreasing due to dielectric breakdown in a portion of a N type drift layer having high concentration formed in an active region near field oxide film corner portions surrounding an gate width end portion. The field oxide film corner portions are disposed on the outside of the gate width end portion so as to be further away from a P type body layer formed in the gate width end portion by forming the active region wider on the outside of the gate width end portion than in a gate width center portion. By this, the N type drift layer having high concentration near the field oxide film corner portions are disposed further away from the P type body layer without increasing the device area.
摘要翻译：本发明防止DMOS晶体管的源极 - 漏极击穿电压由于在围绕栅极宽度端部的场氧化物膜角部附近的有源区域中形成的具有高浓度的N型漂移层的部分中的电介质击穿而减小。通过在栅极宽度端部的外侧形成更宽的有源区域，将场氧化膜角部设置在栅极宽度端部的外侧，以便进一步远离形成在栅极宽度端部的P型主体层部分比在门宽中心部分。由此，在场氧化膜角部附近具有高浓度的N型漂移层配置为远离P型体层而不增加器件面积。

2. 发明申请

US20090278200A1 TRANSISTOR, SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：晶体管，半导体器件及其制造方法
公开(公告)号：US20090278200A1
公开(公告)日：2009-11-12
申请号：US12434128
申请日：2009-05-01
申请人： Yasuhiro TAKEDA , Seiji OTAKE , Kazunori FUJITA
发明人： Yasuhiro TAKEDA , Seiji OTAKE , Kazunori FUJITA
IPC分类号： H01L29/78 , H01L21/20 , H01L21/22
CPC分类号： H01L21/823456 , H01L21/2815 , H01L21/823412 , H01L21/823487 , H01L29/0653 , H01L29/0878 , H01L29/41766 , H01L29/4236 , H01L29/42376 , H01L29/66734 , H01L29/7809 , H01L29/7813
摘要： An ON resistance of a trench gate type transistor and a withstand voltage of a planar type transistor are optimized at the same time. Each of first and second regions of a semiconductor layer is formed by epitaxial growth on each of first and second regions of a semiconductor substrate, respectively. A first buried layer is formed between the first region of the semiconductor substrate and the first region of the semiconductor layer, while a second buried layer is formed between the second region of the semiconductor substrate and the second region of the semiconductor layer. The first buried layer is formed of an N+ type first impurity-doped layer and an N type second impurity-doped layer that extends beyond the fist impurity-doped layer. The second buried layer is formed of an N+ type impurity-doped layer only. In the first region of the semiconductor layer, an impurity is diffused from a surface of the semiconductor layer deep into the semiconductor layer to form an N type third impurity-doped layer. The trench gate type transistor is formed in the first region of the semiconductor layer and the planar type transistor is formed in the second region of the semiconductor layer.
摘要翻译：同时优化沟槽栅型晶体管的导通电阻和平面型晶体管的耐电压。半导体层的第一和第二区域中的每一个分别通过在半导体衬底的第一和第二区域中的每一个上外延生长而形成。在半导体衬底的第一区域和半导体层的第一区域之间形成第一掩埋层，而在半导体衬底的第二区域和半导体层的第二区域之间形成第二掩埋层。第一掩埋层由N +型第一杂质掺杂层和延伸超过第一杂质掺杂层的N型第二杂质掺杂层形成。第二掩埋层仅由N +型杂质掺杂层形成。在半导体层的第一区域中，杂质从半导体层的表面扩散到半导体层中以形成N型第三杂质掺杂层。沟槽栅型晶体管形成在半导体层的第一区域中，并且平面型晶体管形成在半导体层的第二区域中。

3. 发明申请

US20100117726A1 AMPLIFIER APPARATUS 有权
标题翻译：放大器装置
公开(公告)号：US20100117726A1
公开(公告)日：2010-05-13
申请号：US12615687
申请日：2009-11-10
申请人： Yoichi OKUBO , Manabu NAKAMURA , Yasuhiro TAKEDA , Taizo ITO , Junya DOSAKA , Terufumi NAGANO , Hidekatsu UENO , Toshio NOJIMA
发明人： Yoichi OKUBO , Manabu NAKAMURA , Yasuhiro TAKEDA , Taizo ITO , Junya DOSAKA , Terufumi NAGANO , Hidekatsu UENO , Toshio NOJIMA
IPC分类号： H03F3/68
CPC分类号： H03F1/0288
摘要： An amplifier capable of lowering an electrical current flowing in a peak amplifier before a carrier amplifier becomes saturated to thereby improve the efficiency of an entirety of the amplifier is provided. The amplifier includes a carrier amplifier circuit having an amplifying element operable in class-AB or class-B, and a plurality of peak amplifier circuits which have amplifying elements operating in class-B or class-C and which are arranged to start an operation in stages in response to an input level. An output of the carrier amplifier circuit and outputs of the peak amplifier circuits are combined together for signal output. One of the peak amplifier circuits which is rendered operative at the lowest input level is smaller in saturation output than the carrier amplifier circuit.
摘要翻译：提供一种放大器，其能够在载波放大器饱和之前降低在峰值放大器中流动的电流，从而提高整个放大器的效率。放大器包括具有可在AB类或B类中工作的放大元件的载波放大器电路和具有在B类或C类中工作的放大元件的多个峰值放大器电路，响应输入级别的阶段。载波放大器电路的输出和峰值放大器电路的输出被组合在一起用于信号输出。在最低输入电平下工作的峰值放大器电路中的一个在饱和输出中比载波放大器电路小。

4. 发明申请

US20130075865A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130075865A1
公开(公告)日：2013-03-28
申请号：US13612224
申请日：2012-09-12
申请人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
发明人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
IPC分类号： H01L27/06
CPC分类号： H01L27/0259
摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a first P+ type buried layer and a parasitic PNP bipolar transistor which uses a second P+ type buried layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and the first P+ type buried layer as the collector. The first P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, and the parasitic PNP bipolar transistor turns on to flow a large discharge current.
摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和第一P +型掩埋层的PN结二极管和使用连接到P +型扩散层的第二P +型掩埋层的寄生PNP双极晶体管形成作为发射极，以N型外延层为基底，第一P +型埋层作为集电体。第一P +型埋层与阳极连接，P +型扩散层和围绕P +型扩散层的N +型扩散层与阴极电极连接。当向阴极施加大的正静电时，并且寄生PNP双极晶体管导通以流过大的放电电流。

5. 发明申请

US20080220580A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080220580A1
公开(公告)日：2008-09-11
申请号：US12122717
申请日：2008-05-18
申请人： Kunihiko KATO , Masami KOKETSU , Shigeya TOYOKAWA , Keiichi YOSHIZUMI , Hideki YASUOKA , Yasuhiro TAKEDA
发明人： Kunihiko KATO , Masami KOKETSU , Shigeya TOYOKAWA , Keiichi YOSHIZUMI , Hideki YASUOKA , Yasuhiro TAKEDA
IPC分类号： H01L21/8236
CPC分类号： H01L21/823857 , H01L21/823814 , H01L21/823878 , H01L27/0629 , H01L28/40
摘要： A method of manufacturing a semiconductor integrated circuit device having on the same substrate both a high breakdown voltage MISFET and a low breakdown voltage MISFET is provided. An element isolation trench is formed in advance so that the width thereof is larger than the sum of the thickness of a polycrystalline silicon film serving as a gate electrode of a low breakdown voltage, the thickness of a gate insulating film and an alignment allowance in processing of a gate electrode in a direction orthogonal to the extending direction of the gate electrode and is larger than the thickness of the polycrystalline silicon film in a planar region not overlapping the gate electrode. It is possible to decrease the number of manufacturing steps for the semiconductor integrated circuit device.
摘要翻译：提供一种制造半导体集成电路器件的方法，该半导体集成电路器件在相同的衬底上具有高击穿电压MISFET和低击穿电压MISFET。预先形成元件隔离沟槽，使得其宽度大于用作低击穿电压的栅电极的多晶硅膜的厚度，栅绝缘膜的厚度和处理中的对准余量之和在与栅电极的延伸方向正交的方向上的栅电极大于不与栅电极重叠的平面区域中的多晶硅膜的厚度。可以减少半导体集成电路器件的制造步骤的数量。

6. 发明申请

US20080191272A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080191272A1
公开(公告)日：2008-08-14
申请号：US12028585
申请日：2008-02-08
申请人： Yasuhiro TAKEDA
发明人： Yasuhiro TAKEDA
IPC分类号： H01L29/78
CPC分类号： H01L29/4983 , H01L29/0653 , H01L29/086 , H01L29/0878 , H01L29/41766 , H01L29/456 , H01L29/4933 , H01L29/665 , H01L29/66689 , H01L29/7809 , H01L29/7813 , H01L29/7816
摘要： A semiconductor device includes a gate electrode formed through a gate insulating film provided on a first impurity region and a drift layer, and this gate electrode consists of two regions including a first conductivity type second impurity region opposed to the first impurity region and a third impurity region capable of forming a depletion layer.
摘要翻译：半导体器件包括通过设置在第一杂质区域和漂移层上的栅极绝缘膜形成的栅电极，该栅电极由包括与第一杂质区域相对的第一导电型第二杂质区域和第三杂质的两个区域组成能够形成耗尽层的区域。

7. 发明申请

US20130075864A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130075864A1
公开(公告)日：2013-03-28
申请号：US13612194
申请日：2012-09-12
申请人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
发明人： Seiji OTAKE , Yasuhiro TAKEDA , Yuta MIYAMOTO
IPC分类号： H01L27/06
CPC分类号： H01L27/0259
摘要： An ESD protection element is formed by a PN junction diode including an N+ type buried layer having a proper impurity concentration and a P+ type buried layer and a parasitic PNP bipolar transistor which uses a P+ type drawing layer connected to a P+ type diffusion layer as the emitter, an N− type epitaxial layer as the base, and a P type semiconductor substrate as the collector. The P+ type buried layer is connected to an anode electrode, and the P+ type diffusion layer and an N+ type diffusion layer connected to and surrounding the P+ type diffusion layer are connected to a cathode electrode. When a large positive static electricity is applied to the cathode electrode, the parasitic PNP bipolar transistor turns on to flow a large discharge current.
摘要翻译： ESD保护元件由包括具有适当杂质浓度的N +型掩埋层和P +型掩埋层的PN结二极管和使用连接到P +型扩散层的P +型绘图层的寄生PNP双极晶体管形成，作为作为基极的N型外延层和作为集电体的P型半导体基板。 P +型埋层与阳极连接，P +型扩散层与P +型扩散层连接并围绕P +型扩散层的N +型扩散层与阴极电极连接。当向阴极施加大的正静电时，寄生PNP双极晶体管导通以流过大的放电电流。

8. 发明申请

US20120025305A1 BIDIRECTIONAL SWITCH 有权
标题翻译：双向开关
公开(公告)号：US20120025305A1
公开(公告)日：2012-02-02
申请号：US13188059
申请日：2011-07-21
申请人： Yasuhiro TAKEDA
发明人： Yasuhiro TAKEDA
IPC分类号： H01L29/78
CPC分类号： H01L29/7825 , H01L21/2815 , H01L29/42376
摘要： An ON resistance of a bidirectional switch with a trench gate structure composed of two MOS transistors sharing a common drain is reduced. A plurality of trenches is formed in an N type well layer. Then a P type body layer is formed in every other column of the N type well layer interposed between a pair of the trenches. A first N+ type source layer and a second N+ type source layer are formed alternately in each of a plurality of the P type body layers. A first gate electrode is formed in each of a pair of the trenches interposing the first N+ type source layer, and a second gate electrode is formed in each of a pair of the trenches interposing the second N+ type source layer. A portion of the N type well layer interposed between a sidewall on an opposite side of the body layer of the trench in which the first gate electrode is formed and a sidewall on an opposite side of the body layer of the trench in which the second gate electrode is formed makes an N type drain layer serving as an electric field relaxation layer. A cross-sectional area of the N type drain layer makes a path of the ON current.
摘要翻译：具有由共用共同漏极的两个MOS晶体管组成的沟槽栅极结构的双向开关的导通电阻减小。在N型阱层中形成多个沟槽。然后，在插入在一对沟槽之间的N型阱层的每隔一列中形成P型体层。第一N +型源极层和第二N +型源极层在多个P型体层中的每一个中交替地形成。在插入第一N +型源极层的一对沟槽中的每一个中形成第一栅电极，并且在插入第二N +型源极层的一对沟槽中的每一个中形成第二栅电极。 N型阱层的一部分插入在形成有第一栅极的沟槽的主体层的相对侧上的侧壁与沟槽的主体层的相对侧上的侧壁之间，第二栅极电极形成为用作电场弛豫层的N型漏极层。 N型漏极层的横截面积形成导通电流的路径。

9. 发明申请

US20120126324A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120126324A1
公开(公告)日：2012-05-24
申请号：US13303850
申请日：2011-11-23
申请人： Yasuhiro TAKEDA , Shinya Inoue , Yuzo Otsuru
发明人： Yasuhiro TAKEDA , Shinya Inoue , Yuzo Otsuru
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66689
摘要： The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N− type semiconductor layer. A source layer including an N− type layer is disposed in a surface portion of the body layer. An N− type drift layer is formed in a surface portion of the N− type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
摘要翻译：本发明提供了一种LDMOS晶体管，其中由于在栅极绝缘膜中捕获热电子而导致的性能的时间依赖性降低。主体层设置在N-型半导体层的表面部分中。包括N型层的源极层设置在主体层的表面部分中。在N-型半导体层的表面部分形成有N型漂移层。该漂移层包括具有第一N型杂质浓度峰值区域的第一区域和位于比第一N型杂质浓度峰值区域更深的第二N型杂质浓度峰值区域的第二区域，与该第一区域相邻的第二区域。在第二区域的表面部分中形成N +型漏极层。

10. 发明申请

US20120112240A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120112240A1
公开(公告)日：2012-05-10
申请号：US13286832
申请日：2011-11-01
申请人： Yasuhiro TAKEDA , Seiji OTAKE
发明人： Yasuhiro TAKEDA , Seiji OTAKE
IPC分类号： H01L29/739
CPC分类号： H01L29/7816 , H01L29/0873 , H01L29/0878 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7823 , H01L29/7835
摘要： An N type layer made of an N type epitaxial layer in which an N+ type drain layer etc are formed is surrounded by a P type drain isolation layer extending from the front surface of the N type epitaxial layer to an N+ type buried layer. A P type collector layer is formed in an N type layer made of the N type epitaxial layer surrounded by the P type drain isolation layer and a P type element isolation layer, extending from the front surface to the inside of the N type layer. A parasitic bipolar transistor that uses the first conductive type drain isolation layer as the emitter, the second conductive type N type layer as the base, and the collector layer as the collector is thus formed so as to flow a surge current into a ground line.
摘要翻译：由形成有N +型漏极层等的N型外延层构成的N型层由从N型外延层的前表面延伸到N +型掩埋层的P型漏极隔离层包围。在由P型漏极隔离层包围的N型外延层构成的N型层和从N型层的前表面延伸到内部的P型元件隔离层形成P型集电极层。因此，形成使用第一导电型漏极隔离层作为发射极，第二导电型N型层作为基极的集电极层作为集电极的寄生双极型晶体管，以将浪涌电流流入地线。

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