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1. 发明授权

US08198926B2 Loop type clock adjustment circuit and test device 失效
标题翻译：回路类型时钟调节电路和测试装置
公开(公告)号：US08198926B2
公开(公告)日：2012-06-12
申请号：US12936680
申请日：2009-04-07
申请人： Kazuhiro Fujita , Kazuhiro Yamamoto , Masakatsu Suda
发明人： Kazuhiro Fujita , Kazuhiro Yamamoto , Masakatsu Suda
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/093 , H03L7/18
摘要： A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter.
摘要翻译：可变延迟电路将对应于模拟信号的可变延迟应用于参考时钟，以便产生延迟的时钟。相位检测单元检测延迟时钟和参考时钟之间的相位差，并产生具有与相位差对应的电平的相位差信号。计数器根据相位差信号的电平执行计数上升操作或倒计时操作。数字/模拟转换器将计数器的计数值转换为模拟信号，并将所转换的计数值提供给可变延迟电路。计数器包括：第一计数器，配置为使用第一温度计代码根据相位差信号计数计数值的较低位数; 配置为使用第二温度计代码根据所述相位差信号计数所述计数值的上位组的第二计数器; 以及控制电路，被配置为执行控制操作，使得即使在第一计数器和第二计数器的进位操作和借位操作中，汉明距离也保持在1。

2. 发明申请

US20110089983A1 LOOP TYPE CLOCK ADJUSTMENT CIRCUIT AND TEST DEVICE 失效
标题翻译：环路类型时钟调整电路和测试设备
公开(公告)号：US20110089983A1
公开(公告)日：2011-04-21
申请号：US12936680
申请日：2009-04-07
申请人： Kazuhiro Fujita , Kazuhiro Yamamoto , Masakatsu Suda
发明人： Kazuhiro Fujita , Kazuhiro Yamamoto , Masakatsu Suda
IPC分类号： H03L7/08
CPC分类号： H03L7/0812 , H03L7/093 , H03L7/18
摘要： A variable delay circuit applies a variable delay that corresponds to an analog signal to a reference clock so as to generate a delayed clock. A phase detection unit detects the phase difference between the delayed clock and the reference clock, and generates a phase difference signal having a level that corresponds to the phase difference. A counter performs a counting up operation or a counting down operation according to the level of the phase difference signal. A digital/analog converter converts the count value of the counter into an analog signal, and supplies the count value thus converted to the variable delay circuit. The counter comprises: a first counter configured to use a first thermometer code to count the lower group of digits of the count value according to the phase difference signal; a second counter configured to use a second thermometer code to count an upper group of digits of the count value according to the phase difference signal; and a control circuit configured to perform a control operation such that the Hamming distance is maintained at 1 even in a carry operation and a borrow operation of the first counter and the second counter.
摘要翻译：可变延迟电路将对应于模拟信号的可变延迟应用于参考时钟，以便产生延迟的时钟。相位检测单元检测延迟时钟和参考时钟之间的相位差，并产生具有与相位差对应的电平的相位差信号。计数器根据相位差信号的电平执行计数上升操作或倒计时操作。数字/模拟转换器将计数器的计数值转换为模拟信号，并将所转换的计数值提供给可变延迟电路。计数器包括：第一计数器，配置为使用第一温度计代码根据相位差信号计数计数值的较低位数; 配置为使用第二温度计代码根据所述相位差信号计数所述计数值的上位组的第二计数器; 以及控制电路，被配置为执行控制操作，使得即使在第一计数器和第二计数器的进位操作和借位操作中，汉明距离也保持在1。

3. 发明授权

US07987062B2 Delay circuit, test apparatus, storage medium semiconductor chip, initializing circuit and initializing method 失效
标题翻译：延迟电路，测试装置，存储介质半导体芯片，初始化电路和初始化方法
公开(公告)号：US07987062B2
公开(公告)日：2011-07-26
申请号：US11763448
申请日：2007-06-15
申请人： Kazuhiro Fujita , Masakatsu Suda , Takuya Hasumi
发明人： Kazuhiro Fujita , Masakatsu Suda , Takuya Hasumi
IPC分类号： G01R29/02
CPC分类号： G01R31/3016
摘要： A delay circuit includes a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value. The initializing section includes a first loop path that inputs an output signal of the first delay element into the first delay element and a second loop path that inputs an output signal of the second delay element into the second delay element. The initialization section includes a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element, a second measuring section that measures a delay amount in the second delay element, and a delay amount computing section that corrects a delay amount measured by the first measuring section.
摘要翻译：延迟电路包括第一延迟元件，第二延迟元件和初始化部分，其测量由第一延迟元件相对于每个延迟设定值产生的延迟量。初始化部分包括将第一延迟元件的输出信号输入到第一延迟元件中的第一环路径和将第二延迟元件的输出信号输入到第二延迟元件的第二环路径。所述初始化部包括：第一测量部，其顺序地设定与所述第一延迟元件中的所述延迟设定值相互不同的延迟设定值，并且依次测量所述第一延迟元件中的延迟量;测量所述第二延迟中的延迟量的第二测量部元件和延迟量计算部分，其校正由第一测量部分测量的延迟量。

4. 发明申请

US20080048750A1 DELAY CIRCUIT, TEST APPARATUS, STORAGE MEDIUM SEMICONDUCTOR CHIP, INITIALIZING CIRCUIT AND INITIALIZING METHOD 失效
标题翻译：延迟电路，测试装置，存储介质半导体芯片，初始化电路和初始化方法
公开(公告)号：US20080048750A1
公开(公告)日：2008-02-28
申请号：US11763448
申请日：2007-06-15
申请人： Kazuhiro Fujita , Masakatsu Suda , Takuya Hasumi
发明人： Kazuhiro Fujita , Masakatsu Suda , Takuya Hasumi
IPC分类号： H03H11/26
CPC分类号： G01R31/3016
摘要： There is provided a delay circuit including a first delay element, a second delay element, and an initializing section that measures a delay amount generated by the first delay element with respect to each delay setting value and initializes the first delay element. The initializing section includes: a first loop path that inputs an output signal of the first delay element into the first delay element; a second loop path that inputs an output signal of the second delay element into the second delay element; a first measuring section that sequentially sets delay setting values mutually different from the delay setting value in the first delay element and sequentially measures delay amounts in the first delay element; a second measuring section that measures a delay amount in the second delay element; and a delay amount computing section that corrects a delay amount measured by the first measuring section.
摘要翻译：提供了包括第一延迟元件，第二延迟元件和初始化部分的延迟电路，该初始化部分测量由第一延迟元件相对于每个延迟设置值产生的延迟量并初始化第一延迟元件。初始化部分包括：第一循环路径，其将第一延迟元件的输出信号输入到第一延迟元件; 第二循环路径，其将所述第二延迟元件的输出信号输入到所述第二延迟元件中; 第一测量部分，顺序地设置与第一延迟元件中的延迟设定值相互不同的延迟设定值，并顺序地测量第一延迟元件中的延迟量; 第二测量部，其测量第二延迟元件中的延迟量; 以及延迟量计算部，其校正由所述第一测量部测量的延迟量。

5. 发明申请

US20110109377A1 SEMICONDUCTOR INTEGRATED CIRCUIT 失效
标题翻译：半导体集成电路
公开(公告)号：US20110109377A1
公开(公告)日：2011-05-12
申请号：US12996756
申请日：2008-06-09
申请人： Tasuku Fujibe , Yoshihito Nagata , Masakatsu Suda
发明人： Tasuku Fujibe , Yoshihito Nagata , Masakatsu Suda
IPC分类号： G05F1/10
CPC分类号： G06F1/3203 , G01R31/31721 , G01R31/31922
摘要： A circuit block operates while receiving a clock from an external circuit. A load balance circuit is connected to a shared power supply terminal together with the circuit block, and provides predetermined power consumption. A clock detection unit detects input of the clock from an external circuit. When the clock detection unit detects stopping of input of the clock, the load balance circuit is switched to the active state.
摘要翻译：电路块在从外部电路接收时钟时工作。负载平衡电路与电路块一起连接到共享电源端子，并提供预定的功率消耗。时钟检测单元从外部电路检测时钟的输入。当时钟检测单元检测到时钟的输入停止时，负载平衡电路被切换到活动状态。

6. 发明授权

US07908110B2 Test device, test method and computer readable media 失效
标题翻译：测试设备，测试方法和计算机可读介质
公开(公告)号：US07908110B2
公开(公告)日：2011-03-15
申请号：US12177169
申请日：2008-07-22
申请人： Masakatsu Suda
发明人： Masakatsu Suda
IPC分类号： G06F19/00
CPC分类号： G01R31/31932 , G01R31/31727
摘要： Provided is a test apparatus, including a storage section that stores a count value for adjusting a phase of a sampling clock indicating a timing of acquiring an output signal of a DUT; a clock generating section that generates the sampling clock indicating the timing of acquiring the output signal, based on an offset corresponding to the count value and on a reference clock; a first delay section that outputs a first delay clock having a frequency equal to the frequency of the sampling clock and a preset phase difference in relation to the sampling clock, based on the reference clock and the offset; a phase detecting section that detects a phase difference between the first delay clock and a transition point of the output signal, and changes the count value in a direction that decreases the phase difference; a timing comparison section that acquires the output signal according to a transition timing of the sampling clock; and a judging section that judges acceptability of the acquired output signal by comparing the output signal to an expected value.
摘要翻译：提供了一种测试装置，包括存储部分，其存储用于调整指示DUT的输出信号的定时的采样时钟的相位的计数值; 时钟生成部，其基于与计数值对应的偏移和基准时钟，生成表示获取输出信号的定时的采样时钟; 第一延迟部，其基于所述参考时钟和所述偏移，输出具有与所述采样时钟的频率相等的频率的第一延迟时钟和相对于所述采样时钟的预设相位差; 相位检测部，其检测所述第一延迟时钟与所述输出信号的转变点之间的相位差，并且使所述计数值在减小所述相位差的方向上变化; 定时比较部，根据采样时钟的转换定时取得输出信号; 以及判断部，其通过将输出信号与期望值进行比较来判断所获取的输出信号的可接受性。

7. 发明申请

US20090256577A1 Delay Lock Loop Circuit, Timing Generator, Semiconductor Test Device, Semiconductor Integrated Circuit, and Delay Amount Calibration Method 失效
标题翻译：延迟锁定环路，定时发生器，半导体测试器件，半导体集成电路和延迟量校准方法
公开(公告)号：US20090256577A1
公开(公告)日：2009-10-15
申请号：US12083577
申请日：2006-10-18
申请人： Takuya Hasumi , Masakatsu Suda
发明人： Takuya Hasumi , Masakatsu Suda
IPC分类号： H01H31/02 , H03L7/06 , H01L25/00
CPC分类号： H04L7/0337 , H03K5/133 , H03K2005/00026 , H03K2005/00097 , H03L7/0812 , H03L7/087 , H03L7/091
摘要： A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and on the basis of this cycle slip detection signal, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. On the other hand, if any cycle slip is not caused, the counter set value is locked, thereby terminating the process.
摘要翻译：一种方法代替延迟量测量，其中通过替代延迟量的测量的技术来确定计数器的初始设定值，从而可以减少校准延迟电路所需的时间。加载多个计数器设定值的一个计数器设定值，延迟锁定环路电路切换到锁定模式，并且循环滑移检测电路的顺序电路被复位。此后，读取从序列电路输出的周期滑移检测信号，根据该周期滑移检测信号，判断延迟电路的输出信号是否导致周期滑移。如果造成循环滑移，则切换计数器设定值。另一方面，如果没有引起任何循环滑移，则计数器设定值被锁定，从而终止该过程。

8. 发明授权

US07511547B2 Delay circuit, and testing apparatus 失效
标题翻译：延时电路和测试仪器
公开(公告)号：US07511547B2
公开(公告)日：2009-03-31
申请号：US11446855
申请日：2006-06-05
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , G01R31/3191 , G01R31/31922 , G01R31/31937 , H03K2005/00026 , H03K2005/00039 , H03K2005/00058 , H03K2005/0013 , H03K2005/00202 , H03K2005/00267
摘要： A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current. The control section may generate a first control voltage to operate a first MOS transistor in a saturation region and provide the same to a gate terminal of the first MOS transistor.
摘要翻译：提供了一种用于根据期望的延迟时间设置延迟输入信号并将其输出的延迟电路。延迟电路包括：延迟元件，用于基于给定的电源电流延迟输入信号的延迟时间并输出; 用于产生电源电流的电流供应部分; 电压产生部分，用于根据延迟时间设置产生基极电压; 以及控制部分，用于将基极电压转换为取决于电流供应部分的特性的控制电压，并将其提供给电流供应部分，以使电流供应部分产生供电电流。电流供应部分可以具有预定的导电性，并且包括用于将漏极电流施加到延迟元件作为电源电流的第一MOS晶体管。控制部分可以产生第一控制电压以在饱和区域中操作第一MOS晶体管，并将其提供给第一MOS晶体管的栅极端子。

9. 发明申请

US20060267656A1 Delay circuit, and testing apparatus 失效
公开(公告)号：US20060267656A1
公开(公告)日：2006-11-30
申请号：US11446855
申请日：2006-06-05
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , G01R31/3191 , G01R31/31922 , G01R31/31937 , H03K2005/00026 , H03K2005/00039 , H03K2005/00058 , H03K2005/0013 , H03K2005/00202 , H03K2005/00267
摘要： A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current. The control section may generate a first control voltage to operate a first MOS transistor in a saturation region and provide the same to a gate terminal of the first MOS transistor.

10. 发明授权

US07071746B2 Variable delay circuit 失效
公开(公告)号：US07071746B2
公开(公告)日：2006-07-04
申请号：US10835098
申请日：2004-04-29
申请人： Masakatsu Suda , Satoshi Sudou , Toshiyuki Okayasu
发明人： Masakatsu Suda , Satoshi Sudou , Toshiyuki Okayasu
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , G01R31/31922 , G01R31/31937 , H03K5/135 , H03K2005/00026 , H03L7/0805
摘要： A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay element coupled in parallel to the plural stages of first variable delay elements for delaying the reference clock signal, a phase comparator for comparing the phase of the reference clock signal delayed by the plural stages of first variable delay elements with the phase of the reference clock signal delayed by the second variable delay element, and a delay amount control unit for controlling the delay amount of each of the plural stages of first variable delay elements based on the comparison result of the phase comparator in order that the phase of the reference clock signal delayed by the plural stages of first variable delay elements is substantially the same as the phase of the reference clock signal delayed by the second variable delay element after predetermined cycles.

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