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1. 发明授权

US08604773B2 Receiving apparatus, test apparatus, receiving method, and test method 有权
标题翻译：接收装置，试验装置，接收方法和试验方法
公开(公告)号：US08604773B2
公开(公告)日：2013-12-10
申请号：US12939967
申请日：2010-11-04
申请人： Shusuke Kantake , Hidenobu Matsumura
发明人： Shusuke Kantake , Hidenobu Matsumura
IPC分类号： G01R25/00
CPC分类号： G01R31/31937 , G01R31/31922 , G11C29/56 , G11C29/56012
摘要： Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock.
摘要翻译：提供了一种接收方法和接收装置，包括：多选通产生部分，其生成包括相对于接收信号具有不同相位的多个选通的多选通; 获取部，其使用每个所述闪光灯来获取所述接收信号; 检测部，其基于所述获取部的获取结果来检测所述接收信号的值变化的变化位置; 以及选择部，其选择在从所述变化位置偏移预定相位的位置处使用选通脉冲获取的所述接收信号的值作为接收数据值。接收装置还可以包括：参考时钟产生部分，其生成具有预设周期的参考时钟，并且多选通产生部分为参考时钟的每个脉冲产生多次选通。

2. 发明授权

US07511547B2 Delay circuit, and testing apparatus 失效
标题翻译：延时电路和测试仪器
公开(公告)号：US07511547B2
公开(公告)日：2009-03-31
申请号：US11446855
申请日：2006-06-05
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , G01R31/3191 , G01R31/31922 , G01R31/31937 , H03K2005/00026 , H03K2005/00039 , H03K2005/00058 , H03K2005/0013 , H03K2005/00202 , H03K2005/00267
摘要： A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current. The control section may generate a first control voltage to operate a first MOS transistor in a saturation region and provide the same to a gate terminal of the first MOS transistor.
摘要翻译：提供了一种用于根据期望的延迟时间设置延迟输入信号并将其输出的延迟电路。延迟电路包括：延迟元件，用于基于给定的电源电流延迟输入信号的延迟时间并输出; 用于产生电源电流的电流供应部分; 电压产生部分，用于根据延迟时间设置产生基极电压; 以及控制部分，用于将基极电压转换为取决于电流供应部分的特性的控制电压，并将其提供给电流供应部分，以使电流供应部分产生供电电流。电流供应部分可以具有预定的导电性，并且包括用于将漏极电流施加到延迟元件作为电源电流的第一MOS晶体管。控制部分可以产生第一控制电压以在饱和区域中操作第一MOS晶体管，并将其提供给第一MOS晶体管的栅极端子。

3. 发明申请

US20060267656A1 Delay circuit, and testing apparatus 失效
公开(公告)号：US20060267656A1
公开(公告)日：2006-11-30
申请号：US11446855
申请日：2006-06-05
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： H03H11/26
CPC分类号： H03K5/133 , G01R31/3191 , G01R31/31922 , G01R31/31937 , H03K2005/00026 , H03K2005/00039 , H03K2005/00058 , H03K2005/0013 , H03K2005/00202 , H03K2005/00267
摘要： A delay circuit for delaying an input signal according to a desired delay time setting and outputting the same is provided. The delay circuit includes: a delay element for delaying the input signal for a delay time based on a given supply current and outputting the same; a current supply section for generating a supply current; a voltage generating section for generating a base voltage dependent on a delay time setting; and a control section for converting a base voltage to a control voltage dependent on the characteristic of the current supply section and providing the same to the current supply section in order to cause the current supply section to generate the supply current. The current supply section may have a predetermined conductivity and include a first MOS transistor for applying a drain current to the delay element as the supply current. The control section may generate a first control voltage to operate a first MOS transistor in a saturation region and provide the same to a gate terminal of the first MOS transistor.

4. 发明授权

US07574316B2 Pulse width adjustment circuit, pulse width adjustment method, and test apparatus for semiconductor device 失效
标题翻译：脉冲宽度调整电路，脉冲宽度调整方法及半导体器件测试装置
公开(公告)号：US07574316B2
公开(公告)日：2009-08-11
申请号：US12102540
申请日：2008-04-14
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： G06F19/00
CPC分类号： H03K5/06 , G01R31/31922 , H03K5/26 , H03K2005/00078
摘要： A semiconductor test apparatus to test a semiconductor circuit includes a pattern generator which generates a test pattern for testing the semiconductor circuit, a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern, a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal and outputs the timing signal to the waveform shaper, and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit. The pulse width adjusting circuit includes a first delay circuit which outputs a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit which outputs a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section which, in accordance with the first and second delay signals, generates and outputs the timing signal having a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits.
摘要翻译：用于测试半导体电路的半导体测试装置包括产生用于测试半导体电路的测试图案的图形发生器，根据测试图案对要提供给半导体电路的测试信号进行整形的波形整形器，脉冲宽度调节电路其通过调整输入脉冲信号的脉冲宽度来生成用于确定测试信号的相位的定时信号，并将定时信号输出到波形整形器;以及判断部，其判断半导体电路是否良好或基于从半导体电路输出的输出信号。脉宽调整电路包括：第一延迟电路，其输出通过将脉冲信号延迟一定延迟时间而产生的第一延迟信号;第二延迟电路，输出通过将脉冲信号延迟不同的延迟时间而产生的第二延迟信号第一延迟电路和输出部分，其根据第一和第二延迟信号产生并输出具有对应于分别由第一和第二延迟电路实现的延迟时间之间的差的脉冲宽度的定时信号。

5. 发明申请

US20110115468A1 RECEIVING APPARATUS, TEST APPARATUS, RECEIVING METHOD, AND TEST METHOD 有权
标题翻译：接收装置，测试装置，接收方法和测试方法
公开(公告)号：US20110115468A1
公开(公告)日：2011-05-19
申请号：US12939967
申请日：2010-11-04
申请人： Shusuke KANTAKE , Hidenobu MATSUMURA
发明人： Shusuke KANTAKE , Hidenobu MATSUMURA
IPC分类号： G01R25/00 , G11C7/00
CPC分类号： G01R31/31937 , G01R31/31922 , G11C29/56 , G11C29/56012
摘要： Provided is a receiving method and a receiving apparatus comprising a multi-strobe generating section that generates a multi-strobe including a plurality of strobes having different phases with respect to a reception signal; an acquiring section that acquires the reception signal using each of the strobes; a detecting section that detects a change position at which a value of the reception signal changes, based on the acquisition result of the acquiring section; and a selecting section that selects, as a reception data value, the value of the reception signal acquired using a strobe at a position shifted by a predetermined phase from the change position. The receiving apparatus may further comprise a reference clock generating section that generates a reference clock having a preset period, and the multi-strobe generating section generates the multi-strobe for each pulse of the reference clock.
摘要翻译：提供了一种接收方法和接收装置，包括：多选通产生部分，其生成包括相对于接收信号具有不同相位的多个选通的多选通; 获取部，其使用每个所述闪光灯来获取所述接收信号; 检测部，其基于所述获取部的获取结果来检测所述接收信号的值变化的变化位置; 以及选择部，其选择在从所述变化位置偏移预定相位的位置处使用选通脉冲获取的所述接收信号的值作为接收数据值。接收装置还可以包括：参考时钟产生部分，其生成具有预设周期的参考时钟，并且多选通产生部分为参考时钟的每个脉冲产生多次选通。

6. 发明授权

US07460969B2 Pulse width adjustment circuit, pulse width adjustment method, and test apparatus for semiconductor device 失效
标题翻译：脉冲宽度调整电路，脉冲宽度调整方法及半导体器件测试装置
公开(公告)号：US07460969B2
公开(公告)日：2008-12-02
申请号：US11487897
申请日：2006-07-17
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： G06F19/00
CPC分类号： H03K5/06 , G01R31/31922 , H03K5/26 , H03K2005/00078
摘要： There is provided a pulse width adjusting circuit for generating an output signal by adjusting a pulse width of an input pulse signal and outputting the output signal. The pulse width adjusting circuit includes a first delay circuit to output a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit to output a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section to generate and output the output signal in accordance with the first and second delay signals. Here, the output signal has a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits.
摘要翻译：提供了一种脉冲宽度调节电路，用于通过调节输入脉冲信号的脉冲宽度并输出输出信号来产生输出信号。脉宽调整电路包括第一延迟电路，用于输出通过将脉冲信号延迟一定延迟时间而产生的第一延迟信号;第二延迟电路，用于输出通过将脉冲信号延迟不同的延迟时间而产生的第二延迟信号第一延迟电路和输出部分，用于根据第一和第二延迟信号产生和输出输出信号。这里，输出信号具有对应于分别由第一和第二延迟电路实现的延迟时间之间的差的脉冲宽度。

7. 发明申请

US20080201099A1 PULSE WIDTH ADJUSTMENT CIRCUIT, PULSE WIDTH ADJUSTMENT METHOD, AND TEST APPARATUS FOR SEMICONDUCTOR DEVICE 失效
标题翻译：脉冲宽度调整电路，脉冲宽度调整方法和半导体器件的测试装置
公开(公告)号：US20080201099A1
公开(公告)日：2008-08-21
申请号：US12102540
申请日：2008-04-14
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： G01R31/28
CPC分类号： H03K5/06 , G01R31/31922 , H03K5/26 , H03K2005/00078
摘要： A semiconductor test apparatus to test a semiconductor circuit includes a pattern generator which generates a test pattern for testing the semiconductor circuit, a waveform shaper which shapes a test signal to be supplied to the semiconductor circuit based on the test pattern, a pulse width adjusting circuit which generates a timing signal for determining a phase of the test signal by adjusting a pulse width of an input pulse signal and outputs the timing signal to the waveform shaper, and a judging section which judges whether the semiconductor circuit is good or bad based on an output signal output from the semiconductor circuit. The pulse width adjusting circuit includes a first delay circuit which outputs a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit which outputs a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section which, in accordance with the first and second delay signals, generates and outputs the timing signal having a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits.
摘要翻译：用于测试半导体电路的半导体测试装置包括产生用于测试半导体电路的测试图案的图形发生器，根据测试图案对要提供给半导体电路的测试信号进行整形的波形整形器，脉冲宽度调节电路其通过调整输入脉冲信号的脉冲宽度来生成用于确定测试信号的相位的定时信号，并将定时信号输出到波形整形器;以及判断部，其判断半导体电路是否良好或基于从半导体电路输出的输出信号。脉宽调整电路包括：第一延迟电路，其输出通过将脉冲信号延迟一定延迟时间而产生的第一延迟信号;第二延迟电路，输出通过将脉冲信号延迟不同的延迟时间而产生的第二延迟信号第一延迟电路和输出部分，其根据第一和第二延迟信号产生并输出具有对应于由第一和第二延迟电路分别实现的延迟时间之间的差的脉冲宽度的定时信号。

8. 发明申请

US20110248733A1 TEST APPARATUS AND TEST METHOD 审中-公开
标题翻译：测试装置和测试方法
公开(公告)号：US20110248733A1
公开(公告)日：2011-10-13
申请号：US13023431
申请日：2011-02-08
申请人： Shusuke KANTAKE
发明人： Shusuke KANTAKE
IPC分类号： G01R31/00
CPC分类号： G01R31/31726 , G01R31/31725 , G01R31/31727
摘要： A test apparatus that tests a device under test having a plurality of blocks operating asynchronously, based on a signal received from outside, the test apparatus comprising a plurality of domain test units corresponding respectively to the blocks; and a main body unit that controls the domain test units. The main body unit includes a reference operation clock generating section that generates a reference operation clock supplied to each domain test unit, and a test start signal generating section that generates a test start signal instructing each domain test unit to start the testing. Each domain test unit includes a test clock generating section that generates a test clock based on the reference operation clock, and generates a test signal for testing the corresponding block based on the test clock obtained by the test clock generating section, and each domain test unit starts generating the test signal on a condition that the test start signal is received.
摘要翻译：一种测试装置，其基于从外部接收的信号来测试具有异步操作的多个块的被测设备，所述测试设备包括分别对应于所述块的多个域测试单元; 以及控制域测试单元的主体单元。主体单元包括产生提供给每个域测试单元的参考操作时钟的参考操作时钟生成部分，以及生成指示每个域测试单元开始测试的测试开始信号的测试开始信号生成部。每个域测试单元包括测试时钟产生部分，其基于参考操作时钟生成测试时钟，并且基于由测试时钟产生部分获得的测试时钟产生用于测试相应块的测试信号，并且每个域测试单元在接收到测试开始信号的条件下开始产生测试信号。

9. 发明授权

US07549099B2 Testing apparatus and testing method 有权
标题翻译：检测仪器及检测方法
公开(公告)号：US07549099B2
公开(公告)日：2009-06-16
申请号：US11083114
申请日：2005-03-17
申请人： Shusuke Kantake
发明人： Shusuke Kantake
IPC分类号： G06F11/277 , G06F11/36
CPC分类号： G01R31/31932 , G01R31/2882
摘要： A testing apparatus includes a logic comparing unit for comparing the output value with a predetermined expectation value; a pass/fail determining module for determining pass/fail of the device under test based on the comparison result of the logic comparing unit; and a clock generating circuit including a first phase comparing unit for comparing phase of the output data of the device under test with that of the reproduced clock and outputting a first comparison result signal; a second phase comparing unit for comparing phase of the reference clock with that of the reproduced clock and outputting a second comparison result signal; and a reproduced clock generating module for generating the reproduced clock based on the first and second comparison result signals.
摘要翻译：测试装置包括用于将输出值与预定期望值进行比较的逻辑比较单元; 用于根据逻辑比较单元的比较结果确定被测设备的通过/失败的通过/失败确定模块; 以及时钟发生电路，包括：第一相位比较单元，用于比较被测设备的输出数据与再生时钟的输出数据的相位，并输出第一比较结果信号; 第二相位比较单元，用于比较参考时钟的相位与再生时钟的相位，并输出第二比较结果信号; 以及再现时钟产生模块，用于基于第一和第二比较结果信号产生再生时钟。

10. 发明申请

US20080018371A1 Pulse width adjustment circuit, pulse width adjustment method, and test apparatus for semiconductor device 失效
公开(公告)号：US20080018371A1
公开(公告)日：2008-01-24
申请号：US11487897
申请日：2006-07-17
申请人： Masakatsu Suda , Shusuke Kantake
发明人： Masakatsu Suda , Shusuke Kantake
IPC分类号： H03K7/08
CPC分类号： H03K5/06 , G01R31/31922 , H03K5/26 , H03K2005/00078
摘要： There is provided a pulse width adjusting circuit for generating an output signal by adjusting a pulse width of an input pulse signal and outputting the output signal. The pulse width adjusting circuit includes a first delay circuit to output a first delay signal generated by delaying the pulse signal by a certain delay time, a second delay circuit to output a second delay signal generated by delaying the pulse signal by a different delay time from the first delay circuit, and an output section to generate and output the output signal in accordance with the first and second delay signals. Here, the output signal has a pulse width corresponding to a difference between the delay times respectively achieved by the first and second delay circuits.

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