专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4095407A Oscillating and dividing circuit having level shifter for electronic timepiece 失效
标题翻译：具有电子时钟电平转换器的振荡分频电路
公开(公告)号：US4095407A
公开(公告)日：1978-06-20
申请号：US702603
申请日：1976-07-06
申请人： Kazuhiro Asano , Kojiro Tanaka
发明人： Kazuhiro Asano , Kojiro Tanaka
IPC分类号： G04G3/02 , G04G3/00 , G04G9/00 , G04C3/00 , H03K17/60
CPC分类号： G04G9/0047 , G04G3/00
摘要： An oscillation and dividing circuit having a level shifter for an electric timepiece comprises an oscillating circuit, a multi-stage dividing circuit for dividing the frequency of the oscillating circuit and a delay circuit. The outputs of the dividing circuit and the delay circuit are connected through a NAND circuit to the base of a P-FET of the level shifter circuit. The output of the oscillating circuit is connected through an inverter to one input terminal of the first stage of the dividing circuit and through a second inverter to the other input terminal. The output of one stage of the dividing circuit is connected as a control circuit to the delay circuit, thereby supplying a square wave control signal even if the oscillating circuit produces a distorted signal. The pulse width of the pulse applied to the level-shifter is hence constant in spite of poor functioning of the oscillating circuit and a high output voltage is attained.
摘要翻译：具有用于电子钟表的电平移位器的振荡和分频电路包括振荡电路，用于分频振荡电路的频率的多级分频电路和延迟电路。分频电路和延迟电路的输出通过NAND电路连接到电平移位器电路的P-FET的基极。振荡电路的输出通过反相器连接到分频电路的第一级的一个输入端，并通过第二反相器连接到另一输入端。分频电路的一级的输出作为控制电路连接到延迟电路，从而即使振荡电路产生失真信号，也提供方波控制信号。尽管施加到电平移位器的脉冲的脉冲宽度是恒定的，尽管振荡电路的功能差，并且获得高的输出电压。

2. 发明授权

US4386423A Electronic timepiece having multi-functions 失效
标题翻译：电子钟表具有多功能
公开(公告)号：US4386423A
公开(公告)日：1983-05-31
申请号：US49477
申请日：1979-06-18
申请人： Seiko Sasaki , Kazuhiro Asano
发明人： Seiko Sasaki , Kazuhiro Asano
IPC分类号： G04F10/00 , G04G13/02 , G04G15/00 , G04G99/00 , G04B23/02 , G04F5/00
CPC分类号： G04G99/006 , G04G13/02 , G04G15/006
摘要： An electronic timepiece having multi-functions comprises a quartz oscillation circuit as a time standard signal generating circuit, a dividing circuit for dividing the output signal of said quartz oscillation circuit, a timing pulse generating circuit for generating a timing pulse signal which operates many kinds of circuit blocks as an input signal of one part of the output of said dividing circuit, a ROM-circuit as a program memory for executing multi-function operations of the timepiece and others, a program counter and page counter for renewing an address of said ROM-circuit, a RAM-circuit as a data-memory for memorizing a controlling memory, an operated result and a time information, an operation circuit for executing many kinds of operations, a data comparison and a data transformation, a latch circuit as an output data memory circuit for temporarily memorizing a display data or other necessary output data, a driver circuit for displaying all of or a part of the contents of said latch circuit, an alarm sound combining circuit in which a part of the output signal of said dividing circuit can be applied thereto, and wherein at least a part of the address of said program memory is synchronously driven by a 100 HZ signal.
摘要翻译：具有多功能的电子钟表包括作为时间标准信号发生电路的石英振荡电路，用于分割所述石英振荡电路的输出信号的分频电路，产生定时脉冲信号的定时脉冲发生电路，该定时脉冲信号操作多种电路块作为所述分频电路输出的一部分的输入信号，ROM电路作为程序存储器，用于执行钟表等的多功能操作;程序计数器和页计数器，用于更新所述ROM的地址电路，作为用于存储控制存储器的数据存储器的RAM电路，操作结果和时间信息，用于执行多种操作的操作电路，数据比较和数据变换，作为输出的锁存电路数据存储电路，用于临时存储显示数据或其他必要的输出数据;驱动器电路，用于显示所述内容的全部或一部分锁存电路，其中所述分割电路的输出信号的一部分可以被施加到其上的报警声组合电路，并且其中所述程序存储器的地址的至少一部分由100HZ信号同步驱动。

3. 发明授权

US4044544A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4044544A
公开(公告)日：1977-08-30
申请号：US653621
申请日：1976-01-29
申请人： Kenjiro Yagi , Kazuhiro Asano
发明人： Kenjiro Yagi , Kazuhiro Asano
IPC分类号： G04G5/00 , G04G5/02 , G04G5/04 , H01H9/16 , G04B27/08 , G04C3/00
CPC分类号： G04G5/02 , G04G5/045
摘要： An electronic timepiece of the type having a display and a time-correcting switch for effecting correction of the displayed time is provided with a safety switch for enabling and disenabling the time-correcting switch. Whenever the safety switch is switched so as to enable the time-correcting switch, the displayed time on the display panel flashes at one second intervals thereby providing a visual indication of the enabled state of the time-correcting switch to thereby alert the timepiece user that actuation of the time-contacting switch will effect a time correction.
摘要翻译：具有用于进行显示时间校正的具有显示器和时间校正开关的类型的电子钟表设置有用于启用和禁用时间校正开关的安全开关。无论何时切换安全开关以启用时间校正开关，显示面板上显示的时间以一秒的间隔闪烁，从而提供时间校正开关的使能状态的可视指示，从而向钟表用户警告时间接触开关的致动将实现时间校正。

4. 发明授权

US4262346A Multi function electronic timepiece 失效
标题翻译：多功能电子钟表
公开(公告)号：US4262346A
公开(公告)日：1981-04-14
申请号：US49476
申请日：1979-06-18
申请人： Seiko Sasaki , Kazuhiro Asano
发明人： Seiko Sasaki , Kazuhiro Asano
IPC分类号： G04G3/02 , G04G13/02 , G04G15/00 , G04G99/00 , G06F15/02 , G04B3/12
CPC分类号： G04G15/006 , G04G13/02 , G04G3/025
摘要： Circuitry for reducing power consumption in a multi function electronic timepiece utilizes a low frequency signal from the timing pulse generating circuit and a halt signal from the time signal processing circuitry to inhibit the feeding of timing signals to the processing circuitry after the receipt of a halt signal signifying the end of a function routine and until the receipt of the next low frequency signal.
摘要翻译：用于降低多功能电子钟表中的功耗的电路利用来自定时脉冲发生电路的低频信号和来自时间信号处理电路的停止信号，以在接收到停止信号之后禁止向处理电路馈送定时信号表示功能程序的结束，直到接收到下一个低频信号。

5. 发明授权

US4257116A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4257116A
公开(公告)日：1981-03-17
申请号：US906552
申请日：1978-05-16
申请人： Kazuhiro Asano , Seiko Sasaki
发明人： Kazuhiro Asano , Seiko Sasaki
IPC分类号： G04G5/00 , G04G5/04 , G04G99/00 , G04C17/00 , G04F8/00 , G04C15/00
CPC分类号： G04G99/006 , G04G5/04
摘要： An electronic timepiece having a control circuit for controlling operation of the timepiece circuit, and an input switching circuit. The input switching circuit includes a plurality of manually operable switches, and a programmed logic array for receiving signals from the manually operating switches and for developing output signals applied to the control circuit for controlling the control circuit. The input switching circuit further includes a memory having an input for receiving output signals from the programmed logic array, and an output for applying memory output signals to the input of the programmed logic array. The memory has a delay for delaying control of the control circuit, in response to actuation of the manually operable switches, for an interval sufficient to allow an operation being performed by the timepiece circuit to be completed without being interrupted by actuation of the manually operable switches.
摘要翻译：一种电子钟表，具有用于控制钟表电路的动作的控制电路和输入切换电路。输入切换电路包括多个可手动操作的开关，以及编程逻辑阵列，用于接收来自手动操作开关的信号，并用于产生施加到控制电路的用于控制控制电路的输出信号。输入切换电路还包括具有用于接收来自编程逻辑阵列的输出信号的输入的存储器和用于将存储器输出信号施加到编程逻辑阵列的输入的输出。存储器具有延迟控制电路的控制，响应于手动操作的开关的致动而延迟一段间隔，该间隔足以允许由钟表电路执行的操作而不被手动操作的开关的致动而中断。

6. 发明授权

US4205369A Voltage dropping circuit 失效
标题翻译：降压电路
公开(公告)号：US4205369A
公开(公告)日：1980-05-27
申请号：US876369
申请日：1978-02-09
申请人： Kazuhiro Asano
发明人： Kazuhiro Asano
IPC分类号： H02M3/07 , H02M7/00
CPC分类号： H02M3/07
摘要： This invention provides a voltage dropping circuit which is composed of capacitors and MOS field effect electronic switching elements whereby a voltage equal to M/N of the voltage of a power source is obtained.
摘要翻译：本发明提供一种由电容器和MOS场效应电子开关元件组成的降压电路，从而获得等于电源电压的M / N的电压。

7. 发明授权

US4104864A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4104864A
公开(公告)日：1978-08-08
申请号：US739855
申请日：1976-11-09
申请人： Takehiro Ishikawa , Kazumasa Yasuda , Kazuhiro Asano , Takashi Ishijima
发明人： Takehiro Ishikawa , Kazumasa Yasuda , Kazuhiro Asano , Takashi Ishijima
IPC分类号： G04F10/00 , G04G9/00 , G04G9/08 , G04G99/00 , G04F10/04 , G04B19/22 , G04F7/04
CPC分类号： G04G9/087 , G04G9/0076
摘要： An electronic timepiece comprising in combination: the first and secondary time counters, each having the function of 2, 4 hour measuring, which measures the signal of frequency which will be the basis for time measurement; the chronograph, having the function of 24 hour measuring to make the time measurement by measuring the signal of frequency which will be the basis for the above mentioned time measurement; and the display selecting circuit for displaying each enumerated data of the above mentioned first and secondary time counters and the chronograph selectively by the display device.
摘要翻译：一种电子钟表，包括：第一和第二时间计数器，每个具有2,4小时测量功能，测量作为时间测量基础的频率信号; 具有24小时测量功能的计时码表，通过测量作为上述时间测量基础的频率信号进行时间测量; 以及显示选择电路，用于通过显示装置选择性地显示上述第一和第二时间计数器的每个枚举数据和计时器。

8. 发明授权

US06398482B2 Workpiece handling device 失效
标题翻译：工件处理装置
公开(公告)号：US06398482B2
公开(公告)日：2002-06-04
申请号：US09900114
申请日：2001-07-09
申请人： Kazuhiro Asano , Toru Okabe , Kimio Nozaki
发明人： Kazuhiro Asano , Toru Okabe , Kimio Nozaki
IPC分类号： B65G118
CPC分类号： B23P15/26 , B23P19/001 , B23P19/04
摘要： For handling elongate and flat workpieces flowing in a manufacturing line, two arrangements are disclosed, one being an arrangement including a workpiece posture changing device which changes the posture of each workpiece at the time when the workpiece is transmitted from a first conveyer to a second conveyer, and the other being an arrangement for bundling the workpiece flowing in the manufacturing line.
摘要翻译：为了处理在生产线上流动的细长和平坦的工件，公开了两种布置，一种是包括工件姿态改变装置的装置，该工件姿态改变装置在工件从第一输送机传送到第二输送机时改变每个工件的姿态另一个是用于捆扎在生产线上流动的工件的布置。

9. 发明授权

US06276513B1 Workpiece handling device 失效
标题翻译：工件处理装置
公开(公告)号：US06276513B1
公开(公告)日：2001-08-21
申请号：US09414167
申请日：1999-10-08
申请人： Kazuhiro Asano , Toru Okabe , Kimio Nozaki
发明人： Kazuhiro Asano , Toru Okabe , Kimio Nozaki
IPC分类号： B65G4724
CPC分类号： B23P15/26 , B23P19/001 , B23P19/04
摘要： For handling elongate and flat workpieces flowing in a manufacturing line, two arrangements are disclosed, one being an arrangement including a workpiece posture changing device which changes the posture of each workpiece at the time when the workpiece is transmitted from a first conveyer to a second conveyer, and the other being an arrangement for bundling the workpiece flowing in the manufacturing line.
摘要翻译：为了处理在生产线上流动的细长和平坦的工件，公开了两种布置，一种是包括工件姿态改变装置的装置，该工件姿态改变装置在工件从第一输送机传送到第二输送机时改变每个工件的姿态另一个是用于捆扎在生产线上流动的工件的布置。

10. 发明授权

US4312059A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4312059A
公开(公告)日：1982-01-19
申请号：US898439
申请日：1978-04-20
申请人： Masaaki Mandai , Akira Torisawa , Makoto Ueda , Kazuhiro Asano , Masaharu Shida , Katsuhiko Satoh
发明人： Masaaki Mandai , Akira Torisawa , Makoto Ueda , Kazuhiro Asano , Masaharu Shida , Katsuhiko Satoh
IPC分类号： G04C3/14 , H02P8/02 , H02P8/16 , G04F5/00 , G04C19/00 , G05B19/40
CPC分类号： H02P8/16 , G04C3/143
摘要： In an electronic timepiece, a motor is driven by a pulse having a shorter pulse width than the conventional driving pulse and afterwards, a detection pulse is applied to the motor coil so as to determine rotation of the rotor. If the rotor fails to rotate a correction is effected by driving the motor by a pulse having a pulse width greater than the normal driving pulse.
摘要翻译：在电子钟表中，通过脉冲宽度比以往的驱动脉冲短的脉冲来驱动电动机，之后，向电动机线圈施加检测脉冲，以确定转子的旋转。如果转子不能旋转，则通过用脉冲宽度大于正常驱动脉冲的脉冲来驱动电动机来实现校正。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式