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1. 发明授权

US4262347A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4262347A
公开(公告)日：1981-04-14
申请号：US906559
申请日：1978-05-16
申请人： Seiko Sasaki , Kazuhiro Asano
发明人： Seiko Sasaki , Kazuhiro Asano
IPC分类号： G04D7/00 , G04G5/00 , G04G99/00 , G11C29/00 , G11C29/56 , G04C15/00
CPC分类号： G04G99/006 , G04D7/002
摘要： An electronic timepiece including a ROM program memory for storing a program, a program counter for addressing the program memory, and a RAM data memory. An operating circuit including an arithmetic logic circuit operates on the data. The ROM program memory circuit stores a test program, and the program counter includes preset test means for addressing the test program stored in the ROM program circuit to operate the timepiece according to the test program. The program memory counter also includes jump inhibiting means for inhibiting execution of the operating program stored in the ROM program memory, in response to a jump address.
摘要翻译：一种包括用于存储程序的ROM程序存储器，用于寻址程序存储器的程序计数器和RAM数据存储器的电子表。包括算术逻辑电路的操作电路对数据进行操作。 ROM程序存储电路存储测试程序，并且程序计数器包括用于寻址存储在ROM程序电路中的测试程序的预设测试装置，以根据测试程序操作该时计。程序存储计数器还包括响应于跳转地址而禁止执行存储在ROM程序存储器中的操作程序的跳转禁止装置。

2. 发明授权

US4224789A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4224789A
公开(公告)日：1980-09-30
申请号：US906562
申请日：1978-05-16
申请人： Seiko Sasaki , Kazuhiro Asano
发明人： Seiko Sasaki , Kazuhiro Asano
IPC分类号： G04F10/00 , G04G5/00 , G04G99/00 , G04B19/24 , G04B27/00
CPC分类号： G04G99/006
摘要： An electronic timepiece circuit including a data memory for storing time information and display information, and an operating circuit which renews the data stored in the data memory circuit. A program memory circuit stores a sequential program for determining generation of control signals supplied to the data memory circuit and the operating circuit. Two different command data systems are stored in the program memory circuit. One command data system consists of controlling commands which carry out time counting, time setting and display functions, and for pointing addresses in the data memory circuit. The other command data system consists of commands for judging conditions, for pointing addresses of the data memory and for pointing the jump address of the programs stored in the program memory circuit.
摘要翻译：一种电子钟表电路，包括用于存储时间信息和显示信息的数据存储器，以及更新存储在数据存储电路中的数据的操作电路。程序存储电路存储用于确定提供给数据存储电路和操作电路的控制信号的产生的顺序程序。两个不同的命令数据系统存储在程序存储器电路中。一个命令数据系统包括控制执行时间计数，时间设置和显示功能以及数据存储电路中指向地址的命令。另一个命令数据系统包括用于判断条件的命令，用于数据存储器的指向地址和用于指向存储在程序存储器电路中的程序的跳转地址的命令。

3. 发明授权

US4386423A Electronic timepiece having multi-functions 失效
标题翻译：电子钟表具有多功能
公开(公告)号：US4386423A
公开(公告)日：1983-05-31
申请号：US49477
申请日：1979-06-18
申请人： Seiko Sasaki , Kazuhiro Asano
发明人： Seiko Sasaki , Kazuhiro Asano
IPC分类号： G04F10/00 , G04G13/02 , G04G15/00 , G04G99/00 , G04B23/02 , G04F5/00
CPC分类号： G04G99/006 , G04G13/02 , G04G15/006
摘要： An electronic timepiece having multi-functions comprises a quartz oscillation circuit as a time standard signal generating circuit, a dividing circuit for dividing the output signal of said quartz oscillation circuit, a timing pulse generating circuit for generating a timing pulse signal which operates many kinds of circuit blocks as an input signal of one part of the output of said dividing circuit, a ROM-circuit as a program memory for executing multi-function operations of the timepiece and others, a program counter and page counter for renewing an address of said ROM-circuit, a RAM-circuit as a data-memory for memorizing a controlling memory, an operated result and a time information, an operation circuit for executing many kinds of operations, a data comparison and a data transformation, a latch circuit as an output data memory circuit for temporarily memorizing a display data or other necessary output data, a driver circuit for displaying all of or a part of the contents of said latch circuit, an alarm sound combining circuit in which a part of the output signal of said dividing circuit can be applied thereto, and wherein at least a part of the address of said program memory is synchronously driven by a 100 HZ signal.
摘要翻译：具有多功能的电子钟表包括作为时间标准信号发生电路的石英振荡电路，用于分割所述石英振荡电路的输出信号的分频电路，产生定时脉冲信号的定时脉冲发生电路，该定时脉冲信号操作多种电路块作为所述分频电路输出的一部分的输入信号，ROM电路作为程序存储器，用于执行钟表等的多功能操作;程序计数器和页计数器，用于更新所述ROM的地址电路，作为用于存储控制存储器的数据存储器的RAM电路，操作结果和时间信息，用于执行多种操作的操作电路，数据比较和数据变换，作为输出的锁存电路数据存储电路，用于临时存储显示数据或其他必要的输出数据;驱动器电路，用于显示所述内容的全部或一部分锁存电路，其中所述分割电路的输出信号的一部分可以被施加到其上的报警声组合电路，并且其中所述程序存储器的地址的至少一部分由100HZ信号同步驱动。

4. 发明授权

US4262346A Multi function electronic timepiece 失效
标题翻译：多功能电子钟表
公开(公告)号：US4262346A
公开(公告)日：1981-04-14
申请号：US49476
申请日：1979-06-18
申请人： Seiko Sasaki , Kazuhiro Asano
发明人： Seiko Sasaki , Kazuhiro Asano
IPC分类号： G04G3/02 , G04G13/02 , G04G15/00 , G04G99/00 , G06F15/02 , G04B3/12
CPC分类号： G04G15/006 , G04G13/02 , G04G3/025
摘要： Circuitry for reducing power consumption in a multi function electronic timepiece utilizes a low frequency signal from the timing pulse generating circuit and a halt signal from the time signal processing circuitry to inhibit the feeding of timing signals to the processing circuitry after the receipt of a halt signal signifying the end of a function routine and until the receipt of the next low frequency signal.
摘要翻译：用于降低多功能电子钟表中的功耗的电路利用来自定时脉冲发生电路的低频信号和来自时间信号处理电路的停止信号，以在接收到停止信号之后禁止向处理电路馈送定时信号表示功能程序的结束，直到接收到下一个低频信号。

5. 发明授权

US4257116A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4257116A
公开(公告)日：1981-03-17
申请号：US906552
申请日：1978-05-16
申请人： Kazuhiro Asano , Seiko Sasaki
发明人： Kazuhiro Asano , Seiko Sasaki
IPC分类号： G04G5/00 , G04G5/04 , G04G99/00 , G04C17/00 , G04F8/00 , G04C15/00
CPC分类号： G04G99/006 , G04G5/04
摘要： An electronic timepiece having a control circuit for controlling operation of the timepiece circuit, and an input switching circuit. The input switching circuit includes a plurality of manually operable switches, and a programmed logic array for receiving signals from the manually operating switches and for developing output signals applied to the control circuit for controlling the control circuit. The input switching circuit further includes a memory having an input for receiving output signals from the programmed logic array, and an output for applying memory output signals to the input of the programmed logic array. The memory has a delay for delaying control of the control circuit, in response to actuation of the manually operable switches, for an interval sufficient to allow an operation being performed by the timepiece circuit to be completed without being interrupted by actuation of the manually operable switches.
摘要翻译：一种电子钟表，具有用于控制钟表电路的动作的控制电路和输入切换电路。输入切换电路包括多个可手动操作的开关，以及编程逻辑阵列，用于接收来自手动操作开关的信号，并用于产生施加到控制电路的用于控制控制电路的输出信号。输入切换电路还包括具有用于接收来自编程逻辑阵列的输出信号的输入的存储器和用于将存储器输出信号施加到编程逻辑阵列的输入的输出。存储器具有延迟控制电路的控制，响应于手动操作的开关的致动而延迟一段间隔，该间隔足以允许由钟表电路执行的操作而不被手动操作的开关的致动而中断。

6. 发明授权

US4468133A Electronic timepiece 失效
标题翻译：电子钟表
公开(公告)号：US4468133A
公开(公告)日：1984-08-28
申请号：US575485
申请日：1984-01-31
申请人： Seiko Sasaki
发明人： Seiko Sasaki
IPC分类号： G04G9/08 , G04G99/00 , G04F5/00
CPC分类号： G04G99/006 , G04G9/087
摘要： An electronic timepiece has a reference signal generator for generating a 1/10 seconds reference signal which is fed to a static counter which counts the 1/10 seconds reference signal and produces a reference count signal. A read only memory stores a system program which executes and controls a time count. An arithmetic and logic unit executes the time count and a random access memory stores the time counting data. A bidirectional data bus line is connected between the random access memory and the static counter, and a decoder is connected to the bidirectional data bus line for decoding the contents of both the random access memory and the static counter and providing corresponding decoded time data signals. A display device responds to the decoded time data signals and indicates the contents of the random access memory and the static counter. A control circuit is connected to the read only memory and coacts therewith to initiate the actions of the randon access memory and the arithmetic and logic unit in response to the reference count signal from the static counter.
摘要翻译：电子钟表具有用于产生1/10秒基准信号的参考信号发生器，该参考信号被馈送到计数1/10秒参考信号并产生参考计数信号的静态计数器。只读存储器存储执行和控制时间计数的系统程序。算术和逻辑单元执行时间计数，随机存取存储器存储计时数据。双向数据总线连接在随机存取存储器和静态计数器之间，解码器连接到双向数据总线，用于对随机存取存储器和静态计数器的内容进行解码并提供对应的解码时间数据信号。显示装置响应于解码的时间数据信号并且指示随机存取存储器和静态计数器的内容。控制电路连接到只读存储器并与其共同响应来自静态计数器的参考计数信号来启动随机存取存储器和算术和逻辑单元的动作。

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