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1. 发明授权

US08570065B2 Programmable LSI 有权
标题翻译：可编程LSI
公开(公告)号：US08570065B2
公开(公告)日：2013-10-29
申请号：US13437961
申请日：2012-04-03
申请人： Hidetomo Kobayashi , Masami Endo , Yutaka Shionoiri , Hiroki Dembo , Tatsuji Nishijima , Kazuaki Ohshima , Seiichi Yoneda , Jun Koyama
发明人： Hidetomo Kobayashi , Masami Endo , Yutaka Shionoiri , Hiroki Dembo , Tatsuji Nishijima , Kazuaki Ohshima , Seiichi Yoneda , Jun Koyama
IPC分类号： H03K19/177 , G11C11/24
CPC分类号： H03K19/17796 , G11C16/0433 , H01L27/11803 , H01L27/1203
摘要： A low-power programmable LSI that can perform dynamic configuration is provided. The programmable LSI includes a plurality of logic elements. The plurality of logic elements each include a configuration memory. Each of the plurality of logic elements performs different arithmetic processing and changes an electrical connection between the logic elements, in accordance with the configuration data stored in the configuration memory. The configuration memory includes a set of a volatile storage circuit and a nonvolatile storage circuit. The nonvolatile storage circuit includes a transistor whose channel is formed in an oxide semiconductor layer and a capacitor whose one of a pair of electrodes is electrically connected to a node that is set in a floating state when the transistor is turned off.
摘要翻译：提供了可以执行动态配置的低功耗可编程LSI。可编程LSI包括多个逻辑元件。多个逻辑元件各自包括配置存储器。多个逻辑元件中的每一个执行不同的运算处理，并且根据存储在配置存储器中的配置数据改变逻辑元件之间的电连接。配置存储器包括一组易失性存储电路和非易失性存储电路。非易失性存储电路包括其沟道形成在氧化物半导体层中的晶体管和一对电极中的一个电极与晶体管截止时被设置为浮置状态的节点电连接的电容器。

2. 发明授权

US09336845B2 Register circuit including a volatile memory and a nonvolatile memory 有权
标题翻译：包括易失性存储器和非易失性存储器的寄存器电路
公开(公告)号：US09336845B2
公开(公告)日：2016-05-10
申请号：US13467403
申请日：2012-05-09
申请人： Kazuaki Ohshima , Hidetomo Kobayashi
发明人： Kazuaki Ohshima , Hidetomo Kobayashi
IPC分类号： G11C5/06 , G11C11/00 , G11C19/28 , G11C11/404 , G11C14/00 , H01L27/12
CPC分类号： G11C11/005 , G11C11/404 , G11C14/0009 , G11C19/287 , H01L27/1225
摘要： A semiconductor device capable of assessing and rewriting data at a desired timing is provided. A semiconductor device includes a register circuit, a bit line, and a data line. The register circuit includes a flip-flop circuit, a selection circuit, and a nonvolatile memory circuit electrically connected to the flip-flop circuit through the selection circuit. The data line is electrically connected to the flip-flop circuit. The bit line is electrically connected to the nonvolatile memory circuit through the selection circuit. The selection circuit selectively stores data based on a potential of the data line or a potential of the bit line in the nonvolatile memory circuit.
摘要翻译：提供能够在期望的时刻评估和重写数据的半导体器件。半导体器件包括寄存器电路，位线和数据线。寄存器电路包括触发器电路，选择电路和通过选择电路电连接到触发器电路的非易失性存储器电路。数据线电连接到触发器电路。位线通过选择电路电连接到非易失性存储器电路。选择电路基于数据线的电位或非易失性存储器电路中的位线的电位有选择地存储数据。

3. 发明授权

US09059704B2 Programmable logic device 有权
标题翻译：可编程逻辑器件
公开(公告)号：US09059704B2
公开(公告)日：2015-06-16
申请号：US13477192
申请日：2012-05-22
申请人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
发明人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
IPC分类号： G06F1/00 , H03K19/177 , H03K19/173 , G06F3/06
CPC分类号： H03K19/173 , G06F1/3243 , G06F3/0679 , H03K19/17772 , Y02D10/152
摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
摘要翻译：目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

4. 发明申请

US20120311365A1 PROGRAMMABLE LOGIC DEVICE 有权
标题翻译：可编程逻辑器件
公开(公告)号：US20120311365A1
公开(公告)日：2012-12-06
申请号：US13477192
申请日：2012-05-22
申请人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
发明人： Seiichi Yoneda , Jun Koyama , Yutaka Shionoiri , Masami Endo , Hiroki Dembo , Tatsuji Nishijima , Hidetomo Kobayashi , Kazuaki Ohshima
IPC分类号： G06F1/32
CPC分类号： H03K19/173 , G06F1/3243 , G06F3/0679 , H03K19/17772 , Y02D10/152
摘要： An object is to provide a programmable logic device configured to keep a connection state of logic circuits even while power supply voltage is stopped. The programmable logic device includes arithmetic circuits each of whose logic state can be changed; a configuration changing circuit changing the logic states of the arithmetic circuits; a power supply control circuit controlling supply of power supply voltage to the arithmetic circuits; a state memory circuit storing data on the logic states and data on states of the power supply voltage of the arithmetic circuits; and an arithmetic state control circuit controlling the configuration changing circuit and the power supply control circuit in accordance with the data stored in the state memory circuit. A transistor in which a channel formation region is formed in an oxide semiconductor layer is provided between the configuration changing circuit and each of the arithmetic circuits.
摘要翻译：目的是提供一种可编程逻辑器件，其被配置为即使在电源电压停止时仍保持逻辑电路的连接状态。可编程逻辑器件包括可以改变其逻辑状态的运算电路; 配置改变电路改变运算电路的逻辑状态; 电源控制电路，控制对所述运算电路的电源电压供给; 存储关于逻辑状态的数据的状态存储电路和关于运算电路的电源电压的状态的数据; 以及算术状态控制电路，根据存储在状态存储电路中的数据控制配置改变电路和电源控制电路。在配置改变电路和每个运算电路之间设置有在氧化物半导体层中形成沟道形成区的晶体管。

5. 发明授权

US09489830B2 Communication method and communication system 有权
标题翻译：通信方式和通信系统
公开(公告)号：US09489830B2
公开(公告)日：2016-11-08
申请号：US13488873
申请日：2012-06-05
申请人： Kazuaki Ohshima , Hidetomo Kobayashi
发明人： Kazuaki Ohshima , Hidetomo Kobayashi
IPC分类号： G08C17/00 , G08C19/28 , G08C19/22 , G11C5/06 , G11C15/04
CPC分类号： G06K7/10158 , G06K7/10366 , G08C17/00
摘要： A command sequence is restarted from the middle even when supply of power supply voltage to an internal circuit in a wireless tag is temporarily stopped (a power flicker occurs). A register or a cache memory included in a signal processing circuit in the wireless tag continues to retain data even after the supply of power supply voltage is stopped. After the power flicker occurs, the signal processing circuit in the wireless tag is returned to the state before the supply of power supply voltage is stopped and can restart signal processing. Consequently, the command sequence can be restarted from the middle.
摘要翻译：即使暂时停止向无线标签中的内部电路供电电源（发生电源闪烁），也从中间重新启动命令序列。包括在无线标签中的信号处理电路中的寄存器或高速缓冲存储器即使在停止供电电压之后也继续保留数据。在发生电源闪烁之后，无线标签中的信号处理电路返回到电源电压停止之前的状态，并且可以重启信号处理。因此，可以从中间重新启动命令序列。

6. 发明申请

US20120313762A1 Communication Method and Communication System 有权
标题翻译：通信方法与通信系统
公开(公告)号：US20120313762A1
公开(公告)日：2012-12-13
申请号：US13488873
申请日：2012-06-05
申请人： Kazuaki Ohshima , Hidetomo Kobayashi
发明人： Kazuaki Ohshima , Hidetomo Kobayashi
IPC分类号： G08C17/02
CPC分类号： G06K7/10158 , G06K7/10366 , G08C17/00
摘要： A command sequence is restarted from the middle even when supply of power supply voltage to an internal circuit in a wireless tag is temporarily stopped (a power flicker occurs). A register or a cache memory included in a signal processing circuit in the wireless tag continues to retain data even after the supply of power supply voltage is stopped. After the power flicker occurs, the signal processing circuit in the wireless tag is returned to the state before the supply of power supply voltage is stopped and can restart signal processing. Consequently, the command sequence can be restarted from the middle.
摘要翻译：即使暂时停止向无线标签中的内部电路供电电源（发生电源闪烁），也从中间重新启动命令序列。包括在无线标签中的信号处理电路中的寄存器或高速缓冲存储器即使在停止供电电压之后也继续保留数据。在发生电源闪烁之后，无线标签中的信号处理电路返回到电源电压停止之前的状态，并且可以重启信号处理。因此，可以从中间重新启动命令序列。

7. 发明授权

US08243863B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08243863B2
公开(公告)日：2012-08-14
申请号：US12553131
申请日：2009-09-03
申请人： Hidetomo Kobayashi
发明人： Hidetomo Kobayashi
IPC分类号： H04B1/10
CPC分类号： G06K19/0723 , H04B5/0031 , H04B5/0037 , H04L27/04 , H04L27/06 , H04Q2213/13095
摘要： To provide a semiconductor device which can transmit/receive data to/from a reader/writer without interruption of operation by the reader/writer or the like. A semiconductor device capable of wireless communication includes an antenna circuit, a first demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% to 100%, both inclusive, a second demodulation signal generation circuit which demodulates a signal whose modulation factor is from 95% and 100%, both inclusive and from 10% and 30%, both inclusive and a logic circuit which selects one of a demodulation signal from the first circuit and a demodulation signal from the second circuit. When the antenna circuit receives an electromagnetic wave, the logic circuit selects the demodulation signal from the second circuit, and when the antenna circuit transmits an electromagnetic wave, the logic circuit selects the demodulation signal from the first circuit.
摘要翻译：提供一种可以在读取器/写入器等不中断操作的情况下向/从读取器/写入器发送/接收数据的半导体器件。能够进行无线通信的半导体装置包括：天线电路，对调制度为95％〜100％的信号进行解调的第一解调信号生成电路，第二解调信号生成电路，对调制度为 95％和100％，包括10％和30％，以及选择来自第一电路的解调信号和来自第二电路的解调信号之一的逻辑电路。当天线电路接收到电磁波时，逻辑电路从第二电路中选择解调信号，当天线发送电磁波时，逻辑电路从第一电路中选择解调信号。

8. 发明授权

US08209645B2 System and method for converting a synchronous functional circuit to an asynchronous functional circuit 有权
标题翻译：将同步功能电路转换为异步功能电路的系统和方法
公开(公告)号：US08209645B2
公开(公告)日：2012-06-26
申请号：US12565955
申请日：2009-09-24
申请人： Hidetomo Kobayashi
发明人： Hidetomo Kobayashi
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A hierarchizing means 101 for blocking, of a first description which represents a functional circuit in an RTL, a second description and for converting the first description into a hierarchized third description; a first logic synthesis means 102 for logic synthesis of the third description; a first placement and routing means 103 for first placement and routing; a first substitution means 104 for substituting a fourth description indicating the unit circuit which is asynchronous for the second description; a second logic synthesis means 105 for logic synthesis of the fourth description; a second placement and routing means 106 for second placement and routing; a calculation means 107 for calculating a circuit on which the second placement and routing is performed; and a second substitution means 108 for substituting the circuit on which placement and routing is performed by the second placement and routing means 106 for a selected circuit on which placement and routing is performed by the first placement and routing means 103.
摘要翻译：用于阻止表示RTL中的功能电路的第一描述的第二描述和用于将第一描述转换为层次化的第三描述的层次化装置101; 用于第三描述的逻辑合成的第一逻辑合成装置102; 用于第一布置和布线的第一放置和布线装置103; 第一替代装置104，用于代替指示第二描述异步的单元电路的第四描述; 用于第四描述的逻辑合成的第二逻辑合成装置105; 用于第二布置和布线的第二布置和布线装置106; 用于计算执行第二布置和布线的电路的计算装置107; 以及第二替代装置108，用于代替由第二布置和布线装置106对由第一放置和布线装置103执行放置和布线的所选电路执行放置和布线的电路。

9. 发明授权

US08207756B2 Logic circuit and semiconductor device 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US08207756B2
公开(公告)日：2012-06-26
申请号：US12912397
申请日：2010-10-26
申请人： Yutaka Shionoiri , Hidetomo Kobayashi
发明人： Yutaka Shionoiri , Hidetomo Kobayashi
IPC分类号： H03K19/096
CPC分类号： H01L29/7869 , H01L27/088 , H01L27/1225 , H03K3/0375 , H03K19/0016 , H03K19/096
摘要： In a logic circuit where clock gating is performed, the standby power is reduced or malfunction is suppressed. The logic circuit includes a transistor which is in an off state where a potential difference exists between a source terminal and a drain terminal over a period during which a clock signal is not supplied. A channel formation region of the transistor is formed using an oxide semiconductor in which the hydrogen concentration is reduced. Specifically, the hydrogen concentration of the oxide semiconductor is 5×1019 (atoms/cm3) or lower. Thus, leakage current of the transistor can be reduced. As a result, in the logic circuit, reduction in standby power and suppression of malfunction can be achieved.
摘要翻译：在执行时钟门控的逻辑电路中，待机功率降低或故障被抑制。该逻辑电路包括在不提供时钟信号的时段内处于源极端子和漏极端子之间存在电位差的关断状态的晶体管。使用其中氢浓度降低的氧化物半导体形成晶体管的沟道形成区域。具体地说，氧化物半导体的氢浓度为5×1019（原子/ cm3）以下。因此，可以减小晶体管的漏电流。结果，在逻辑电路中，可以实现待机功率的降低和故障的抑制。

10. 发明申请

US20120287703A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120287703A1
公开(公告)日：2012-11-15
申请号：US13467097
申请日：2012-05-09
申请人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
发明人： Hidetomo Kobayashi , Masashi Fujita , Takuro Ohmaru
IPC分类号： G11C11/24
CPC分类号： G06F12/08 , G06F1/3275 , G11C11/005 , G11C11/404 , H01L27/10873 , H01L27/115 , H01L27/11517 , H01L27/1203 , H01L27/1225 , Y02D10/14
摘要： When a CPU provided with a latch memory is operated, a constant storage method or an end storage method is selected depending on what is processed by the CPU; thus, the CPU provided with a latch memory has low power consumption. When the CPU provided with a latch memory is operated, in the case where the number of times of turning on and off the power source is high, a constant storage method is employed and in the case where the number of times of turning on and off the power source is low, an end storage method is employed. Whether a constant storage method or an end storage method is selected is determined based on the threshold value set depending on power consumption.
摘要翻译：当具有闩锁存储器的CPU被操作时，根据CPU处理的内容选择恒定存储方法或结束存储方法; 因此，具有闩锁存储器的CPU具有低功耗。当具有闩锁存储器的CPU被操作时，在电源打开和关闭的次数高的情况下，采用恒定的存储方法，并且在打开和关闭的次数的情况下电源低，采用端存储方式。基于根据功耗设定的阈值来确定是否选择恒定存储方法或结束存储方法。

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