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1. 发明申请

US20130019083A1 Redundant Transactional Memory 审中-公开
标题翻译：冗余事务记忆
公开(公告)号：US20130019083A1
公开(公告)日：2013-01-17
申请号：US13179672
申请日：2011-07-11
申请人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
发明人： Harold W. Cain, III , David M. Daly , Kattamuri Ekanadham , Michael C. Huang , Jose E. Moreira , Mauricio J. Serrano
IPC分类号： G06F9/30
CPC分类号： G06F9/30087 , G06F9/3834 , G06F9/3842 , G06F11/1492 , G06F11/1629 , G06F2201/845
摘要： A mechanism is provided for redundant execution of a set of instructions. A redundant execution begin (rbegin) instruction to be executed by a first hardware thread on the first processor is identified in the set of instructions. The set of instructions immediately after the rbegin instruction are executed on the first hardware thread and on a second hardware thread. Responsive to both the first processor and the second processor ending execution of the set of instructions, responsive to a first set of cache lines in a first speculative store matching a second set of cache lines in a second speculative store, and responsive to a first set of register states in a first status register matching a second set of register states in a second status register, dirty lines in the first speculative store are committed thereby committing a redundant transaction state to an architectural state.
摘要翻译：提供了用于一组指令的冗余执行的机制。在该组指令中识别由第一处理器上的第一硬件线程执行的冗余执行开始（rbegin）指令。 rbegin指令之后的指令集在第一个硬件线程和第二个硬件线程上执行。响应于所述第一处理器和所述第二处理器结束所述指令集的执行，响应于在第二推测存储器中匹配第二组高速缓存行的第一推测存储器中的第一组高速缓存行，并响应于第一集合在与第二状态寄存器中的第二组寄存器状态匹配的第一状态寄存器中的寄存器状态被提交，从而将第一推测存储器中的脏线提交给架构状态的冗余事务状态。

2. 发明申请

US20110238962A1 Register Checkpointing for Speculative Modes of Execution in Out-of-Order Processors 审中-公开
标题翻译：在无序处理器中注册执行的投机模式的注册点
公开(公告)号：US20110238962A1
公开(公告)日：2011-09-29
申请号：US12729282
申请日：2010-03-23
申请人： Harold W. Cain, III , Kattamuri Ekanadham , IL Park
发明人： Harold W. Cain, III , Kattamuri Ekanadham , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/384 , G06F9/3842 , G06F9/3863
摘要： A mechanism is provided for generating a checkpoint for a speculatively executed portion of code. The mechanisms identify, during a speculative execution of a portion of code, a register renaming operation occurring to an entry in a register renaming table of the processor. In response to the register renaming operation occurring to the register renaming table, a determination is made as to whether an update to an entry in a hardware-implemented recovery renaming table is to be performed. If so, the entry in the hardware-implemented recovery renaming table is updated. The entry in the recovery renaming table is part of the checkpoint for the speculative execution of the portion of code.
摘要翻译：提供了一种用于生成用于推测性地执行的代码部分的检查点的机制。机构在推测执行代码的一部分期间识别发生在处理器的寄存器重命名表中的条目的寄存器重命名操作。响应于对寄存器重命名表发生的寄存器重命名操作，确定是否执行对硬件实现的恢复重命名表中的条目的更新。如果是这样，则更新硬件实现的恢复重命名表中的条目。恢复重命名表中的条目是对部分代码的推测执行的检查点的一部分。

3. 发明申请

US20110314259A1 OPERATING A STACK OF INFORMATION IN AN INFORMATION HANDLING SYSTEM 有权
标题翻译：在信息处理系统中操作信息堆栈
公开(公告)号：US20110314259A1
公开(公告)日：2011-12-22
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , IL Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

4. 发明申请

US20120239904A1 SEAMLESS INTERFACE FOR MULTI-THREADED CORE ACCELERATORS 有权
标题翻译：多线程加速器的无缝接口
公开(公告)号：US20120239904A1
公开(公告)日：2012-09-20
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作而不会出现内存转换错误在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

5. 发明授权

US08683175B2 Seamless interface for multi-threaded core accelerators 有权
标题翻译：多线程核心加速器的无缝界面
公开(公告)号：US08683175B2
公开(公告)日：2014-03-25
申请号：US13048214
申请日：2011-03-15
申请人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
发明人： Kattamuri Ekanadham , Hung Q. Le , Jose E. Moreira , Pratap C. Pattnaik
IPC分类号： G06F9/30 , G06F12/10
CPC分类号： G06F9/3877 , G06F9/30043 , G06F9/3012 , G06F9/30123 , G06F9/3851 , G06F12/1027
摘要： A method, system and computer program product are disclosed for interfacing between a multi-threaded processing core and an accelerator. In one embodiment, the method comprises copying from the processing core to the hardware accelerator memory address translations for each of multiple threads operating on the processing core, and simultaneously storing on the hardware accelerator one or more of the memory address translations for each of the threads. Whenever any one of the multiple threads operating on the processing core instructs the hardware accelerator to perform a specified operation, the hardware accelerator has stored thereon one or more of the memory address translations for the any one of the threads. This facilitates starting that specified operation without memory translation faults. In an embodiment, the copying includes, each time one of the memory address translations is updated on the processing core, copying the updated one of the memory address translations to the hardware accelerator.
摘要翻译：公开了用于在多线程处理核心和加速器之间进行接口的方法，系统和计算机程序产品。在一个实施例中，该方法包括从处理核心复制到在处理核心上操作的多个线程中的每个线程的硬件加速器存储器地址转换，以及同时在硬件加速器上存储每个线程的一个或多个存储器地址转换。只要在处理核心上操作的多个线程中的任何一个指示硬件加速器执行指定的操作，则硬件加速器在其上存储有针对任何一个线程的一个或多个存储器地址转换。这有助于启动指定的操作，而不会出现内存转换错误。在一个实施例中，复制包括每次在处理核心上更新一个存储器地址转换时，将更新的一个存储器地址转换复制到硬件加速器。

6. 发明授权

US08943299B2 Operating a stack of information in an information handling system 有权
标题翻译：在信息处理系统中操作一堆信息
公开(公告)号：US08943299B2
公开(公告)日：2015-01-27
申请号：US12817609
申请日：2010-06-17
申请人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
发明人： Kattamuri Ekanadham , Brian R. Konigsburg , David S. Levitan , Jose E. Moreira , David Mui , Il Park
IPC分类号： G06F9/30
CPC分类号： G06F9/30 , G06F9/30134 , G06F9/30163 , G06F9/3861
摘要： A pointer is for pointing to a next-to-read location within a stack of information. For pushing information onto the stack: a value is saved of the pointer, which points to a first location within the stack as being the next-to-read location; the pointer is updated so that it points to a second location within the stack as being the next-to-read location; and the information is written for storage at the second location. For popping the information from the stack: in response to the pointer, the information is read from the second location as the next-to-read location; and the pointer is restored to equal the saved value so that it points to the first location as being the next-to-read location.
摘要翻译：一个指针用于指向一堆信息中的下一个读取位置。将信息推送到堆栈中：保存指针的值，该指针指向堆栈内的第一个位置作为下一个读取位置; 指针被更新，使得它指向堆栈内的第二位置作为下一个读取位置; 并且将信息写入第二位置处的存储。为了从堆栈弹出信息：响应于指针，从第二位置读取信息作为下一个读取位置; 并且指针被恢复为等于保存的值，使得其指向作为下一个读取位置的第一位置。

7. 发明申请

US20100287536A1 PROFILING APPLICATION PERFORMANCE ACCORDING TO DATA STRUCTURE 失效
标题翻译：根据数据结构分析应用性能
公开(公告)号：US20100287536A1
公开(公告)日：2010-11-11
申请号：US12436894
申请日：2009-05-07
申请人： I-Hsin Chung , Guojing Cong , Kattamuri Ekanadham , David Klepacki , Simone Sbaraglia , Hui-Fang Wen
发明人： I-Hsin Chung , Guojing Cong , Kattamuri Ekanadham , David Klepacki , Simone Sbaraglia , Hui-Fang Wen
IPC分类号： G06F11/36 , G06F9/44 , G06F9/45
CPC分类号： G06F8/443 , G06F11/3471 , G06F2201/865
摘要： During runtime of a binary program file, streams of instructions are executed and memory references, generated by instrumentation applied to given ones of the instructions that refer to memory locations, are collected. A transformation is performed, based on the executed streams of instructions and the collected memory references, to obtain a table. The table lists memory events of interest for active data structures for each function in the program file. The transformation is performed to translate memory addresses for given ones of the instructions and given ones of the data structures into locations and variable names in a source file corresponding to the binary file. At least the memory events of interest are displayed, and the display is organized so as to correlate the memory events of interest with corresponding ones of the data structures.
摘要翻译：在二进制程序文件的运行期间，执行指令流，并且收集通过应用于指向存储器位置的给定指令的仪器产生的存储器引用。基于所执行的指令流和所收集的存储器引用执行变换以获得表。该表列出了程序文件中每个功能的活动数据结构感兴趣的内存事件。执行转换以将给定的指令的内存地址转换为与二进制文件相对应的源文件中的数据结构中的位置和变量名。至少显示感兴趣的存储器事件，并且显示被组织以使感兴趣的存储器事件与相应的数据结构相关联。

8. 发明授权

US06085295A Method of maintaining data coherency in a computer system having a plurality of interconnected nodes 失效
标题翻译：在具有多个互连节点的计算机系统中维护数据一致性的方法
公开(公告)号：US06085295A
公开(公告)日：2000-07-04
申请号：US954496
申请日：1997-10-20
申请人： Kattamuri Ekanadham , Beng-Hong Lim , Pratap Chandra Pattnaik , Marc Snir
发明人： Kattamuri Ekanadham , Beng-Hong Lim , Pratap Chandra Pattnaik , Marc Snir
IPC分类号： G06F12/08 , G06F12/16
CPC分类号： G06F12/0813 , G06F12/0817 , G06F2212/2542
摘要： A method of providing coherent shared memory access among a plurality of shared memory multiprocessor nodes. For each line of data in each of the nodes, a list of those processors of the node that have copies of the line in their caches is maintained. If a memory command is issued from a processor of one node, and if the command is directed to a line of memory of another node, then the memory command is sent directly to an adapter of the one node. When the adapter receives the command, it forwards the command from the one adapter to another adapter of the other node. When the other adapter receives the command, the command is forwarded to the local memory of the other node. The list of processors is then updated in the local memory of the other node to include or exclude the other adapter depending on the command. If the memory command is issued from one of the processors of one of the nodes, and if the command is directed to a line of memory of the one node, then the command is sent directly to local memory. When the local memory receives the command and if the adapter of the node is in the list of processors for a line associated with the command and if the command is a write command, then the command is forwarded to the adapter of the one node. When the adapter receives the command, the command is forwarded to remote adapters in each of the remote nodes which have processors which have cache copies of the line. Finally, when the latter remote adapters receive the command, the command is forwarded to the processors having the cache copies of the line.
摘要翻译：一种在多个共享存储器多处理器节点之间提供一致的共享存储器访问的方法。对于每个节点中的每一行数据，维护节点中具有其高速缓存中的行的副本的那些处理器的列表。如果从一个节点的处理器发出存储器命令，并且如果命令被定向到另一个节点的存储器行，则存储器命令被直接发送到该一个节点的适配器。当适配器接收到命令时，它将该命令从一个适配器转发到另一个节点的另一个适配器。当另一个适配器接收到该命令时，该命令将转发到另一个节点的本地内存。然后在另一个节点的本地存储器中更新处理器列表，以根据命令包括或排除另一个适配器。如果从其中一个节点的一个处理器发出存储器命令，并且如果命令被定向到一个节点的存储器行，则该命令被直接发送到本地存储器。当本地内存接收到该命令时，如果节点的适配器位于与该命令相关联的一行的处理器列表中，并且该命令是写入命令，则该命令将转发到该一个节点的适配器。当适配器接收到该命令时，该命令将转发到具有具有该行的高速缓存副本的处理器的每个远程节点中的远程适配器。最后，当后一个远程适配器接收到该命令时，该命令被转发到具有该行的缓存副本的处理器。

9. 发明授权

US5408658A Self-scheduling parallel computer system and method 失效
标题翻译：自调并行计算机系统及方法
公开(公告)号：US5408658A
公开(公告)日：1995-04-18
申请号：US730365
申请日：1991-07-15
申请人： Rudolph N. Rechtschaffen , Kattamuri Ekanadham
发明人： Rudolph N. Rechtschaffen , Kattamuri Ekanadham
IPC分类号： G06F9/38 , G06F9/45 , G06F15/16
CPC分类号： G06F9/3808 , G06F8/451 , G06F9/3802 , G06F9/3812 , G06F9/3836 , G06F9/3853 , G06F9/3855 , G06F9/3857
摘要： An incremental method is described for distributing the instructions of an execution sequence among a plurality of processing elements for execution in parallel. The distribution is based upon anticipated availability times of the needed input values for each instruction as well as the anticipated availability times of each processing element for handling each instruction. A self-parallelizing computer system and method are also described for asynchronously processing the distributed instructions in two modes of execution on a set of processing elements which communicate with each other.
摘要翻译：描述了用于在多个处理元件之间并行执行执行序列的指令的分发方法。该分配基于每个指令的所需输入值的预期可用时间以及用于处理每个指令的每个处理元件的预期可用时间。还描述了一种自并行计算机系统和方法，用于在一组彼此通信的处理元件上以两种执行模式异步处理分布式指令。

10. 发明申请

US20110138101A1 MAINTAINING DATA COHERENCE BY USING DATA DOMAINS 失效
标题翻译：通过使用数据域维护数据的一致性
公开(公告)号：US20110138101A1
公开(公告)日：2011-06-09
申请号：US12633428
申请日：2009-12-08
申请人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
发明人： Kattamuri Ekanadham , Il Park , Pratap Pattnaik
IPC分类号： G06F12/06
CPC分类号： G06F9/30007 , G06F12/0817 , G06F12/1027
摘要： A method, system and computer program product are disclosed for maintaining data coherence, for use in a multi-node processing system where each of the nodes includes one or more components. In one embodiment, the method comprises establishing a data domain, assigning a group of the components to the data domain, sending a coherence message from a first component of the processing system to a second component of the processing system, and determining if that second component is assigned to the data domain. In this embodiment, if that second component is assigned to the data domain, the coherence message is transferred to all of the components assigned to the data domain to maintain data coherency among those components. In an embodiment, if that second component is assigned to the data domain, the first component is assigned to the data domain.
摘要翻译：公开了用于维持数据一致性的方法，系统和计算机程序产品，用于多节点处理系统，其中每个节点包括一个或多个组件。在一个实施例中，该方法包括建立数据域，将一组组件分配给数据域，将相干消息从处理系统的第一组件发送到处理系统的第二组件，以及确定该第二组件被分配给数据域。在该实施例中，如果该第二组件被分配给数据域，则将相干消息传送到分配给数据域的所有组件，以维持这些组件之间的数据一致性。在一个实施例中，如果将该第二组件分配给数据域，则将第一组件分配给数据域。

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