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1. 发明申请

US20080027664A1 Architectural Level Throughput Based Power Modeling Methodology and Apparatus for Pervasively Clock-Gated Processor Cores 有权
标题翻译：基于建筑级吞吐量的电力建模方法和设备，用于普适时钟门控处理器内核
公开(公告)号：US20080027664A1
公开(公告)日：2008-01-31
申请号：US11780712
申请日：2007-07-20
申请人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
发明人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
IPC分类号： G01R21/00
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method for estimating power dissipated by a processor core processing a workload-includes analyzing a reference test case to generate a reference workload characteristic, analyzing an actual workload to generate an actual workload characteristic, performing a power analysis for the reference test case to establish a reference power dissipation value and estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value.
摘要翻译：一种用于估计由处理器核心处理工作负载的功率消耗的方法 - 包括分析参考测试用例以生成参考工作负载特征，分析实际工作负载以产生实际工作负载特性，对参考测试用例执行功率分析以建立参考功耗值，并根据实际和参考工作负载特性和参考功耗值估计实际工作负载功耗值。

2. 发明授权

US09311228B2 Power reduction in server memory system 有权
标题翻译：服务器内存系统功耗降低
公开(公告)号：US09311228B2
公开(公告)日：2016-04-12
申请号：US13439457
申请日：2012-04-04
申请人： David M. Daly , Tejas Karkhanis , Valentina Salapura
发明人： David M. Daly , Tejas Karkhanis , Valentina Salapura
IPC分类号： G06F12/00 , G06F12/02 , G06F11/34 , G06F12/06
CPC分类号： G06F12/023 , G06F11/3409 , G06F11/3471 , G06F12/06 , G06F2201/81 , G06F2201/88 , G06F2212/1028 , G06F2212/2532 , G06F2212/502 , Y02D10/13 , Y02D10/34
摘要： A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
摘要翻译：一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法，其经由存储器控制器与存储器芯片无效通信。存储器可以以模式操作，使得经由存储器控制器，存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动，从而导致更少的操作等级。然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。

3. 发明申请

US20110320765A1 VARIABLE WIDTH VECTOR INSTRUCTION PROCESSOR 审中-公开
标题翻译：可变宽度矢量指示处理器
公开(公告)号：US20110320765A1
公开(公告)日：2011-12-29
申请号：US12825328
申请日：2010-06-28
申请人： Tejas Karkhanis , Jose E. Moreira , Valentina Salapura
发明人： Tejas Karkhanis , Jose E. Moreira , Valentina Salapura
IPC分类号： G06F9/30 , G06F15/76
CPC分类号： G06F9/30112 , G06F9/30014 , G06F9/30036 , G06F9/30109 , G06F9/30123 , G06F9/30141 , G06F9/3851 , G06F15/8076
摘要： A computer processor, method, and computer program product for executing vector processing instructions on a variable width vector register file. An example embodiment is a computer processor that includes an instruction execution unit coupled to a variable width vector register file which contains a number of vector registers, the width of the vector registers is changeable during operation of the computer processor.
摘要翻译：一种用于在可变宽度向量寄存器文件上执行矢量处理指令的计算机处理器，方法和计算机程序产品。示例性实施例是一种计算机处理器，其包括耦合到包含多个向量寄存器的可变宽度向量寄存器文件的指令执行单元，在计算机处理器的操作期间向量寄存器的宽度是可变的。

4. 发明申请

US20060080625A1 Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores 有权
标题翻译：基于建筑级吞吐量的功率建模方法和设备，用于普及时钟门控处理器内核
公开(公告)号：US20060080625A1
公开(公告)日：2006-04-13
申请号：US10960730
申请日：2004-10-07
申请人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
发明人： Pradip Bose , Tejas Karkhanis , Srinivasan Ramani , Malcolm Ware , Ken Vu
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F2217/78
摘要： A method, system, and apparatus for estimating the power dissipated by a processor core processing a workload, where the method includes analyzing a reference test case to generate a reference workload characteristic. Analyzing an actual workload to generate an actual workload characteristic. Performing a power analysis for the reference test case to establish a reference power dissipation value. Estimating an actual workload power dissipation value responsive to the actual and reference workload characteristics and the reference power dissipation value
摘要翻译：一种用于估计由处理器核心处理工作负载消耗的功率的方法，系统和装置，其中所述方法包括分析参考测试用例以生成参考工作负载特性。分析实际工作负载以生成实际工作负载特性。对参考测试用例进行功率分析，建立参考功耗值。根据实际和参考工作负载特性以及参考功耗值估算实际工作负载功耗值

5. 发明申请

US20130268741A1 POWER REDUCTION IN SERVER MEMORY SYSTEM 有权
标题翻译：服务器内存系统中的电源减少
公开(公告)号：US20130268741A1
公开(公告)日：2013-10-10
申请号：US13439457
申请日：2012-04-04
申请人： David M. Daly , Tejas Karkhanis , Valentina Salapura
发明人： David M. Daly , Tejas Karkhanis , Valentina Salapura
IPC分类号： G06F12/02
CPC分类号： G06F12/023 , G06F11/3409 , G06F11/3471 , G06F12/06 , G06F2201/81 , G06F2201/88 , G06F2212/1028 , G06F2212/2532 , G06F2212/502 , Y02D10/13 , Y02D10/34
摘要： A system and method for reducing power consumption of memory chips outside of a host processor device inoperative communication with the memory chips via a memory controller. The memory can operate in modes, such that via the memory controller, the stored data can be localized and moved at various granularities, among ranks established in the chips, to result in fewer operating ranks. Memory chips may then be turned on and off based on host memory access usage levels at each rank in the chip. Host memory access usage levels at each rank in the chip is tracked by performance counters established for association with each rank of a memory chip. Turning on and off of the memory chips is based on a mapping maintained between ranks and address locations corresponding to sub-sections within each rank receiving the host processor access requests.
摘要翻译：一种用于降低主处理器设备外部的存储器芯片的功耗的系统和方法，其经由存储器控制器与存储器芯片无效通信。存储器可以以模式操作，使得经由存储器控制器，存储的数据可以在芯片中建立的等级之间以各种粒度进行本地化和移动，从而导致更少的操作等级。然后可以基于芯片中每个级别的主机存储器访问使用级别来打开和关闭存储器芯片。芯片中每个级别的主机存储器访问使用级别由建立用于与存储器芯片的每个等级相关联的性能计数器跟踪。存储器芯片的导通和关闭是基于维持在对应于接收主机处理器访问请求的每个等级内的子部分的地址位置的地址位置之间的映射。

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