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1. 发明授权

US06518629B1 Semiconductor device and process for producing the device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06518629B1
公开(公告)日：2003-02-11
申请号：US09609388
申请日：2000-07-03
申请人： Tomoyoshi Kushida , Katsuhiko Nishiwaki
发明人： Tomoyoshi Kushida , Katsuhiko Nishiwaki
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate electrodes, and an emitter electrode. Strips of the insulation layer extend in a direction intersecting a direction of extension of the gate electrodes, and form a stripe pattern. The insulation layer curbs extraction of holes into the channel region. Openings in the stripe pattern of the insulation layer form depletion layers.
摘要翻译：在具有高电压电阻和低导通电压特性的半导体器件中，在漂移区域中形成电荷存储区域（绝缘层）。形成在漂移区上方的是沟道区，发射极区，沟槽型栅电极和发射极。绝缘层的条带沿着与栅电极的延伸方向相交的方向延伸，并形成条纹图案。绝缘层遏制了孔进入通道区域。绝缘层的条纹图案中的开口形成耗尽层。

2. 发明授权

US06921941B2 High withstand voltage field effect semiconductor device with a field dispersion region 有权
标题翻译：具有场分散区域的高耐压场效应半导体器件
公开(公告)号：US06921941B2
公开(公告)日：2005-07-26
申请号：US10777153
申请日：2004-02-13
申请人： Katsuhiko Nishiwaki , Tomoyoshi Kushida , Sachiko Kawaji
发明人： Katsuhiko Nishiwaki , Tomoyoshi Kushida , Sachiko Kawaji
IPC分类号： H01L29/78 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/73
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0834 , H01L29/66348
摘要： It is intended to provide a high withstand voltage field effect type semiconductor device that relaxes electric fields in a semiconductor substrate without thickening thickness of a drift region and achieves withstand-ability against high voltage without sacrificing ON-voltage, switch-OFF characteristics, and miniaturization. A field effective type semiconductor device comprises emitter regions 100, 104 and gate electrodes 106 and the like on a surface (upper surface in FIG. 2), a collector region 101 and the like on the other surface (lower surface in FIG. 2), wherein N− field dispersion regions 111 of low impurity concentration are arranged between P body regions 103 facing to gate electrodes 106 and an N drift region 102 below P body regions 103. Thereby, electric field between collector and emitter is relaxed and high withstand voltage field effect type semiconductor device is realized. Another field dispersion region can be arranged between the N drift region 102 and P+ collector region 101 below the N drift region 102.
摘要翻译：旨在提供一种在不增加漂移区域的厚度的情况下放松半导体衬底中的电场的高耐压电场场效应型半导体器件，并且在不牺牲接通电压，关断特性和小型化的情况下实现高电压耐受能力。场效应型半导体器件在另一表面（图2中的下表面）上的表面（图2中的上表面）上的发射极区域100,104和栅极电极106等，集电区域101等，其中低杂质浓度的N + - 场色散区域111被布置在面向栅电极106的P体区域103和P体区域103之下的N漂移区域102之间。由此，集电极与发射极之间的电场松弛，实现了高耐受电压场效应型半导体器件。另外的场分散区域可以配置在N漂移区域102之下的N漂移区域102和P + +集电极区域101之间。

3. 发明授权

US06930353B2 Field-effect-type semiconductor device 有权
标题翻译：场效应型半导体器件
公开(公告)号：US06930353B2
公开(公告)日：2005-08-16
申请号：US10694947
申请日：2003-10-29
申请人： Katsuhiko Nishiwaki , Tomoyoshi Kushida
发明人： Katsuhiko Nishiwaki , Tomoyoshi Kushida
IPC分类号： H01L29/78 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/76
CPC分类号： H01L29/0696 , H01L29/0839 , H01L29/7397
摘要： It is intended to provide a field-effective-type semiconductor device that can let low ON-resistance and non-excessive short-circuit current go together by effectively using its channel width and prevents device from destruction. In a field-effective-type semiconductor device, a semiconductor region arranged between gate electrodes 106 has stripe-patterned structure consisting of an N+ emitter region 104 and a P emitter region. The P emitter region is constituted by P channel region 103 of low concentration and P+ emitter region 100 of high concentration. The N+ emitter region 104, the P channel region 103, and the P+ emitter region 100 are in contact with the emitter electrode 109. Thereby, a channel width X is limited to the extent that is enough for ON current under normal operation state. That is, low ON-resistance and not excessive short-circuit current can go together in the field-effective-type semiconductor device.
摘要翻译：旨在提供一种场效应型半导体器件，其可以通过有效地使用其沟道宽度并且防止器件破坏而使低导通电阻和非过度短路电流一起。在现场有效型半导体器件中，布置在栅电极106之间的半导体区域具有由N + +发射极区域104和P发射极区域构成的条纹图案化结构。 P发射极区域由低浓度的P沟道区域103和高浓度的P + +发射极区域100构成。 N +发射极区域104，P沟道区域103和P + +发射极区域100与发射极电极109接触。由此，通道宽度X为限于在正常运行状态下对ON电流足够的程度。也就是说，在场效应型半导体器件中，低导通电阻而不是过度的短路电流可以一起放在一起。

4. 发明授权

US08830114B2 Mobile object detecting apparatus 有权
标题翻译：移动物体检测装置
公开(公告)号：US08830114B2
公开(公告)日：2014-09-09
申请号：US13510638
申请日：2010-09-30
申请人： Tomoyoshi Yasue , Tomoyoshi Kushida
发明人： Tomoyoshi Yasue , Tomoyoshi Kushida
IPC分类号： G01S13/04 , G01S13/56 , G01S13/87 , G01S13/536 , G01S13/00 , G08B13/16
CPC分类号： G01S13/56 , G01S13/04 , G01S13/87 , G08B13/1627
摘要： A mobile object detecting apparatus includes first radiation detecting means; and second radiation detecting means for radiating an electromagnetic wave having the same frequency as the electromagnetic wave radiated by the first radiation detecting means such that the radiated electromagnetic wave passes near a point in the first radiation detecting means from which the electromagnetic wave is radiated, and detecting a standing wave which is generated due to reflection of the radiated electromagnetic wave at an object; wherein a distance, over which the electromagnetic wave radiated by the first radiation detecting means travels until it reaches near the first radiation detecting means, corresponds to a distance of an integral multiple of a wave length of a half cycle of the electromagnetic waves radiated by the radiation detecting means plus a wave length of a predetermined period which is smaller than the half cycle.
摘要翻译：移动物体检测装置包括第一辐射检测装置; 以及第二辐射检测装置，用于辐射具有与由第一辐射检测装置辐射的电磁波相同频率的电磁波，使得辐射电磁波通过靠近辐射电磁波的第一辐射检测装置中的一点;以及检测由于物体处的辐射电磁波的反射而产生的驻波; 其中由第一辐射检测装置辐射的电磁波行进直到其到达第一辐射检测装置附近的距离对应于由第一辐射检测装置辐射的电磁波的半周期的波长的整数倍的距离，辐射检测装置加上小于半周期的预定周期的波长。

5. 发明授权

US5905294A High rated voltage semiconductor device with floating diffusion regions 失效
标题翻译：具有浮动扩散区域的高额定电压半导体器件
公开(公告)号：US5905294A
公开(公告)日：1999-05-18
申请号：US787682
申请日：1997-01-23
申请人： Tomoyoshi Kushida
发明人： Tomoyoshi Kushida
IPC分类号： H01L29/06 , H01L21/265 , H01L21/336 , H01L29/10 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/66712 , H01L29/1095 , H01L29/42324 , H01L29/7802 , H01L21/26586 , H01L29/0619
摘要： A field-effect semiconductor device has a gate pad at the outside of an area of a semiconductor element and island regions of a conductivity type opposite that of a substrate of the device at surfaces of the device under the gate pad. When voltage is applied to the semiconductor device's drain, depletion layers form and extend to the opposite side of the substrate from each of the island regions and become continuous with one another. Thus, the voltage applied to the device's insulation layers is limited and a high rated voltage of the device can be obtained. Further, this arrangement provides a wide contact area between the gate pad and the gate wiring because meshed gate wiring is formed in the area between the island regions. In this way, insulation film having no contact holes in the island regions and contact holes in the body region may be formed without replacing masks by alternating the opening with for introducing impurities in the island region and the opening width in the body region.
摘要翻译：场效应半导体器件在半导体元件的区域的外侧具有栅极焊盘，并且在栅极焊盘下方的器件的表面处具有与器件的衬底的导电类型相反的岛状区域。当电压施加到半导体器件的漏极时，耗尽层从每个岛区域形成并延伸到衬底的相对侧并且彼此连续。因此，施加到器件绝缘层的电压是有限的，并且可以获得器件的高额定电压。此外，这种布置提供了栅极焊盘和栅极布线之间的宽接触面积，因为在岛状区域之间的区域中形成有栅极栅极布线。以这种方式，可以形成在岛状区域中不具有接触孔的绝缘膜和体区域中的接触孔，而不用通过交替开口替换掩模，以在岛区域中引入杂质和体区域中的开口宽度。

6. 发明申请

US20120235850A1 MOBILE OBJECT DETECTING APPARATUS 有权
标题翻译：移动对象检测设备
公开(公告)号：US20120235850A1
公开(公告)日：2012-09-20
申请号：US13510638
申请日：2010-09-30
申请人： Tomoyoshi Yasue , Tomoyoshi Kushida
发明人： Tomoyoshi Yasue , Tomoyoshi Kushida
IPC分类号： G01S13/56
CPC分类号： G01S13/56 , G01S13/04 , G01S13/87 , G08B13/1627
摘要： A mobile object detecting apparatus includes first radiation detecting means ; and second radiation detecting means for radiating an electromagnetic wave having the same frequency as the electromagnetic wave radiated by the first radiation detecting means such that the radiated electromagnetic wave passes near a point in the first radiation detecting means from which the electromagnetic wave is radiated, and detecting a standing wave which is generated due to reflection of the radiated electromagnetic wave at an object; wherein a distance, over which the electromagnetic wave radiated by the first radiation detecting means travels until it reaches near the first radiation detecting means, corresponds to a distance of an integral multiple of a wave length of a half cycle of the electromagnetic waves radiated by the radiation detecting means plus a wave length of a predetermined period which is smaller than the half cycle.
摘要翻译：移动物体检测装置包括第一辐射检测装置; 以及第二辐射检测装置，用于辐射具有与由第一辐射检测装置辐射的电磁波相同频率的电磁波，使得辐射电磁波通过靠近辐射电磁波的第一辐射检测装置中的一点;以及检测由于物体处的辐射电磁波的反射而产生的驻波; 其中由第一辐射检测装置辐射的电磁波行进直到其到达第一辐射检测装置附近的距离对应于由第一辐射检测装置辐射的电磁波的半周期的波长的整数倍的距离，辐射检测装置加上小于半周期的预定周期的波长。

7. 发明授权

US07507646B2 Semiconductor devices and method of manufacturing them 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US07507646B2
公开(公告)日：2009-03-24
申请号：US11436616
申请日：2006-05-19
申请人： Shinya Yamazaki , Tomoyoshi Kushida , Takahide Sugiyama
发明人： Shinya Yamazaki , Tomoyoshi Kushida , Takahide Sugiyama
IPC分类号： H01L21/265
CPC分类号： H01L29/868 , H01L29/32
摘要： With conventional device, the quantity of complex defects differs with each semiconductor device because the concentration of impurities intrinsically contained differs for each silicon wafer. Consequently, there is an undesirable variation in characteristics among the semiconductor devices. The invention provides a method for manufacturing PIN type diode which comprises an intermediate semiconductor region in which complex defects are formed. The method comprises introducing impurities (for example, carbon), which are the sane kind of impurities intrinsically contained in the intermediate semiconductor region, into the intermediate semiconductor region, and irradiating the intermediate semiconductor region with helium ions to form point defects.
摘要翻译：对于常规装置，由于每个硅晶片的固有杂质的浓度不同，所以复合缺陷的数量因每个半导体器件而不同。因此，半导体器件之间的特性存在不期望的变化。本发明提供一种制造PIN型二极管的方法，其包括形成复杂缺陷的中间半导体区域。该方法包括将与中间半导体区域本征含有的相同种类的杂质的杂质（例如碳）引入中间半导体区域，并且用氦离子照射中间半导体区域以形成点缺陷。

8. 发明授权

US07038275B2 Buried-gate-type semiconductor device 有权
标题翻译：埋栅型半导体器件
公开(公告)号：US07038275B2
公开(公告)日：2006-05-02
申请号：US10732350
申请日：2003-12-11
申请人： Tomoyoshi Kushida
发明人： Tomoyoshi Kushida
IPC分类号： H01L29/76
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0878 , H01L29/1095 , H01L29/4236 , H01L29/4238 , H01L29/66348 , H01L29/7392 , H01L29/7397 , H01L29/7722 , H01L29/7828
摘要： An object of this invention is to provide a buried gate-type semiconductor device in which its gate interval is minimized so as to improve channel concentration thereby realizing low ON-resistance, voltage-resistance depression due to convergence of electrical fields in the vicinity of the bottom of the gate is prevented and further prevention of voltage-resistance depression and OFF characteristic are achieved at the same time. A plurality of gate electrodes 106 each having a rectangular section are disposed in its plan section. The interval 106T between the long sides of the gate electrodes 106 is made shorter than the interval 106S between the short sides thereof. Further, a belt-like contact opening 108 is provided between the short sides of the gate electrode 106, so that P+ source region 100 and N+ source region 104 are in contact with a source electrode. Consequently, the interval 106T between the long sides of the gate electrode 106 can be set up regardless of the width of the contact opening 108.
摘要翻译：本发明的一个目的是提供一种掩埋栅极型半导体器件，其栅极间隔被最小化，从而提高沟道浓度，从而实现低导通电阻，由于电场附近的电场会聚而产生的低电压抑制防止栅极的底部，同时进一步防止电压下降和OFF特性。在其平面部分中设置有多个具有矩形截面的栅电极106。使栅电极106的长边之间的间隔106T比其短边之间的间隔106S短。此外，在栅电极106的短边之间设置带状接触开口108，使得源极区100和源极区104源于与源电极接触。因此，无论接触开口108的宽度如何，可以设定栅电极106的长边之间的间隔106T。

9. 发明授权

US06774407B2 Semiconductor device with a suppressed increase in turned-on resistance and an improved turn-off response 失效
标题翻译：具有抑制的导通电阻增加和关断响应改善的半导体器件
公开(公告)号：US06774407B2
公开(公告)日：2004-08-10
申请号：US09751452
申请日：2001-01-02
申请人： Tomoyoshi Kushida
发明人： Tomoyoshi Kushida
IPC分类号： H01L2974
CPC分类号： H01L29/66348 , H01L21/263 , H01L21/26506 , H01L21/26586 , H01L21/266 , H01L29/32 , H01L29/7397
摘要： The present invention provides a semiconductor device wherein the turning-off time thereof can be reduced substantially and, at the same time, the turned-on resistance thereof can also be prevented effectively from increasing as well. Lattice defects are distributed at a high concentration in a defect region an area in close proximity to the boundary surface between an n drift region and a p+ substrate. The half-value width of the distribution is set at a value which is large enough for the defect region to include a non-depletion region in the n drift region. However, the defect region is not spread to cover a diffusion layer. In this way, the turning-off time of the semiconductor device can be reduced considerably without being accompanied by an increase in turned-on resistance thereof. In addition, by employing an absorber with an uneven surface, the distribution of lattice defects can be obtained by carrying out radiation of ions at only one time.
摘要翻译：本发明提供一种半导体器件，其中其截止时间可以大大降低，并且同时也可以有效地防止其导通电阻的增加。晶格缺陷以非常接近于n漂移区和p +衬底之间的边界面的区域在缺陷区域中以高浓度分布。分布的半值宽度被设定为足够大的值，使得缺陷区域在n漂移区域中包括非耗尽区域。然而，缺陷区域不扩散以覆盖扩散层。以这种方式，可以显着降低半导体器件的关断时间，而不伴随着其导通电阻的增加。此外，通过使用具有不平坦表面的吸收体，可以通过仅一次进行离子的辐射来获得晶格缺陷的分布。

10. 发明授权

US5559346A Field-effect semiconductor device with increased breakdown voltage 失效
标题翻译：具有增加的击穿电压的场效半导体器件
公开(公告)号：US5559346A
公开(公告)日：1996-09-24
申请号：US324662
申请日：1994-10-18
申请人： Tomoyoshi Kushida
发明人： Tomoyoshi Kushida
IPC分类号： H01L29/80 , H01L29/739 , H01L29/772 , H01L29/808 , H01L29/74 , H01L31/111
CPC分类号： H01L29/808 , H01L29/7393 , H01L29/7722 , H01L29/8086
摘要： A field-effect semiconductor device for reducing on-state source-drain voltage and increasing breakdown voltage, has a one conductivity type semiconductor region, a source region of one conductivity type, a drain region, and gate regions of other conductivity type. The source region, the drain region and the gate regions are formed in the semiconductor region and contiguous to a surface of the semiconductor region. The gate regions are located so as to sandwich a portion of the semiconductor region coupling the source region and the drain region.
摘要翻译：用于降低导通状态源极 - 漏极电压并增加击穿电压的场效应半导体器件具有一个导电类型的半导体区域，一个导电类型的源极区域，漏极区域和另一个导电类型的栅极区域。源极区域，漏极区域和栅极区域形成在半导体区域中并与半导体区域的表面邻接。栅极区域被定位成夹住耦合源极区域和漏极区域的半导体区域的一部分。

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