专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US06921941B2 High withstand voltage field effect semiconductor device with a field dispersion region 有权
标题翻译：具有场分散区域的高耐压场效应半导体器件
公开(公告)号：US06921941B2
公开(公告)日：2005-07-26
申请号：US10777153
申请日：2004-02-13
申请人： Katsuhiko Nishiwaki , Tomoyoshi Kushida , Sachiko Kawaji
发明人： Katsuhiko Nishiwaki , Tomoyoshi Kushida , Sachiko Kawaji
IPC分类号： H01L29/78 , H01L21/331 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/73
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/0834 , H01L29/66348
摘要： It is intended to provide a high withstand voltage field effect type semiconductor device that relaxes electric fields in a semiconductor substrate without thickening thickness of a drift region and achieves withstand-ability against high voltage without sacrificing ON-voltage, switch-OFF characteristics, and miniaturization. A field effective type semiconductor device comprises emitter regions 100, 104 and gate electrodes 106 and the like on a surface (upper surface in FIG. 2), a collector region 101 and the like on the other surface (lower surface in FIG. 2), wherein N− field dispersion regions 111 of low impurity concentration are arranged between P body regions 103 facing to gate electrodes 106 and an N drift region 102 below P body regions 103. Thereby, electric field between collector and emitter is relaxed and high withstand voltage field effect type semiconductor device is realized. Another field dispersion region can be arranged between the N drift region 102 and P+ collector region 101 below the N drift region 102.
摘要翻译：旨在提供一种在不增加漂移区域的厚度的情况下放松半导体衬底中的电场的高耐压电场场效应型半导体器件，并且在不牺牲接通电压，关断特性和小型化的情况下实现高电压耐受能力。场效应型半导体器件在另一表面（图2中的下表面）上的表面（图2中的上表面）上的发射极区域100,104和栅极电极106等，集电区域101等，其中低杂质浓度的N + - 场色散区域111被布置在面向栅电极106的P体区域103和P体区域103之下的N漂移区域102之间。由此，集电极与发射极之间的电场松弛，实现了高耐受电压场效应型半导体器件。另外的场分散区域可以配置在N漂移区域102之下的N漂移区域102和P + +集电极区域101之间。

2. 发明授权

US06518629B1 Semiconductor device and process for producing the device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06518629B1
公开(公告)日：2003-02-11
申请号：US09609388
申请日：2000-07-03
申请人： Tomoyoshi Kushida , Katsuhiko Nishiwaki
发明人： Tomoyoshi Kushida , Katsuhiko Nishiwaki
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/7397 , H01L29/7813
摘要： In a semiconductor device having high voltage resistance and low ON voltage characteristics, charge-storage regions (insulation layer) are formed in a drift region. Formed above the drift region are a channel region, an emitter region, trench-type gate electrodes, and an emitter electrode. Strips of the insulation layer extend in a direction intersecting a direction of extension of the gate electrodes, and form a stripe pattern. The insulation layer curbs extraction of holes into the channel region. Openings in the stripe pattern of the insulation layer form depletion layers.
摘要翻译：在具有高电压电阻和低导通电压特性的半导体器件中，在漂移区域中形成电荷存储区域（绝缘层）。形成在漂移区上方的是沟道区，发射极区，沟槽型栅电极和发射极。绝缘层的条带沿着与栅电极的延伸方向相交的方向延伸，并形成条纹图案。绝缘层遏制了孔进入通道区域。绝缘层的条纹图案中的开口形成耗尽层。

3. 发明授权

US06930353B2 Field-effect-type semiconductor device 有权
标题翻译：场效应型半导体器件
公开(公告)号：US06930353B2
公开(公告)日：2005-08-16
申请号：US10694947
申请日：2003-10-29
申请人： Katsuhiko Nishiwaki , Tomoyoshi Kushida
发明人： Katsuhiko Nishiwaki , Tomoyoshi Kushida
IPC分类号： H01L29/78 , H01L29/06 , H01L29/08 , H01L29/739 , H01L29/76
CPC分类号： H01L29/0696 , H01L29/0839 , H01L29/7397
摘要： It is intended to provide a field-effective-type semiconductor device that can let low ON-resistance and non-excessive short-circuit current go together by effectively using its channel width and prevents device from destruction. In a field-effective-type semiconductor device, a semiconductor region arranged between gate electrodes 106 has stripe-patterned structure consisting of an N+ emitter region 104 and a P emitter region. The P emitter region is constituted by P channel region 103 of low concentration and P+ emitter region 100 of high concentration. The N+ emitter region 104, the P channel region 103, and the P+ emitter region 100 are in contact with the emitter electrode 109. Thereby, a channel width X is limited to the extent that is enough for ON current under normal operation state. That is, low ON-resistance and not excessive short-circuit current can go together in the field-effective-type semiconductor device.
摘要翻译：旨在提供一种场效应型半导体器件，其可以通过有效地使用其沟道宽度并且防止器件破坏而使低导通电阻和非过度短路电流一起。在现场有效型半导体器件中，布置在栅电极106之间的半导体区域具有由N + +发射极区域104和P发射极区域构成的条纹图案化结构。 P发射极区域由低浓度的P沟道区域103和高浓度的P + +发射极区域100构成。 N +发射极区域104，P沟道区域103和P + +发射极区域100与发射极电极109接触。由此，通道宽度X为限于在正常运行状态下对ON电流足够的程度。也就是说，在场效应型半导体器件中，低导通电阻而不是过度的短路电流可以一起放在一起。

4. 外观设计

USD279780S Facsimile transceiver 失效
公开(公告)号：USD279780S
公开(公告)日：1985-07-23
申请号：US478370
申请日：1983-03-24
申请人： Katsuhiko Nishiwaki , Akitaka Takeuchi , Hiroshi Endo , Akihiro Kawakami , Hideo Matsumura
设计人： Katsuhiko Nishiwaki , Akitaka Takeuchi , Hiroshi Endo , Akihiro Kawakami , Hideo Matsumura

5. 发明授权

US07579652B2 Semiconductor device having a high withstand voltage 有权
标题翻译：具有高耐压的半导体器件
公开(公告)号：US07579652B2
公开(公告)日：2009-08-25
申请号：US10562839
申请日：2004-06-10
申请人： Katsuhiko Nishiwaki
发明人： Katsuhiko Nishiwaki
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/0696 , H01L29/41741 , H01L29/42324
摘要： To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode 106, having N+ emitter region 104 and P+ emitter region 100, and controlling conduction between emitter and collector by voltage applied to gate electrode 106, the shape of contact opening 108 contacting emitter (N+ emitter region 104 and P+ emitter region 100) and emitter electrode is formed of curved lines at four corners. Hence, eliminating right-angle apex, hole current from the field region into the emitter electrode after switching off is prevented from concentrating at one point.
摘要翻译：为了呈现即使在大电流下也能够稳定地工作的半导体器件，通过减小在关断之后的接触开口的角部的电流集中并抑制局部的发热而不增加导通电压。在由P区域111和栅电极106分压的绝缘栅晶体管中，具有N +发射极区域104和P +发射极区域100，并且通过施加到栅电极106的电压来控制发射极和集电极之间的导通，接触开口108的形状与发射极（N +发射极区域104和P +发射极区域100），发射电极由四个角部的曲线形成。因此，在一点上防止从切割角度消除直角顶点，从场区域到发射极电极的空穴电流集中。

6. 发明申请

US20060163653A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060163653A1
公开(公告)日：2006-07-27
申请号：US10562839
申请日：2004-06-10
申请人： Katsuhiko Nishiwaki
发明人： Katsuhiko Nishiwaki
IPC分类号： H01L29/76
CPC分类号： H01L29/0696 , H01L29/41741 , H01L29/42324
摘要： To present a semiconductor device capable of operating stably even at large current, by lessening current concentration into the corners of contact opening after switching off and suppressing local heat generation without raising the ON voltage. In an insulated gate transistor divided by P field region 111 and gate electrode 106, having N+ emitter region 104 and P+ emitter region 100, and controlling conduction between emitter and collector by voltage applied to gate electrode 106, the shape of contact opening 108 contacting emitter (N+ emitter region 104 and P+ emitter region 100) and emitter electrode is formed of curved lines at four corners. Hence, eliminating right-angle apex, hole current from the field region into the emitter electrode after switching off is prevented from concentrating at one point.
摘要翻译：为了呈现即使在大电流下也能够稳定地工作的半导体器件，通过减小在关断之后的接触开口的角部的电流集中并抑制局部的发热而不增加导通电压。在由P区域111和栅电极106分压的绝缘栅晶体管中，具有N +发射极区域104和P +发射极区域100，并且通过施加到栅电极106的电压来控制发射极和集电极之间的导通，接触开口108的形状与发射极（N +发射极区域104和P +发射极区域100），发射电极由四个角部的曲线形成。因此，在一点上防止从切割角度消除直角顶点，从场区域到发射极电极的空穴电流集中。

7. 发明授权

US06509610B2 Insulated gate semiconductor device with high minority carrier injection and low on-voltage by enlarged pn-junction area 失效
公开(公告)号：US06509610B2
公开(公告)日：2003-01-21
申请号：US09906825
申请日：2001-07-18
申请人： Akira Kawahashi , Katsuhiko Nishiwaki
发明人： Akira Kawahashi , Katsuhiko Nishiwaki
IPC分类号： H01L21336
CPC分类号： H01L29/0834 , H01L29/7397
摘要： A semiconductor device is formed such that a contact surface between a p-type high-concentration semiconductor region and an n-type high-concentration buffer region assumes a convexo-concave shape. This makes it possible to enlarge an area of the contact surface between the p-type high-concentration semiconductor region and the n-type high-concentration buffer region. As a result, holes are injected into an n-type low-concentration drift region from the p-type high-concentration semiconductor region with higher efficiency and with a less voltage drop between the pn-junction. Thus, effects of conductivity modulation can be achieved sufficiently and the on-resistance and the voltage drop of an IGBT can be lowered.

8. 外观设计

USD278712S Central processor unit 失效
公开(公告)号：USD278712S
公开(公告)日：1985-05-07
申请号：US444707
申请日：1982-11-26
申请人： Koushirou Adachi , Katsuhiko Nishiwaki , Motoake Sakamoto , Tamotsu Tsukaguchi , Mitsuo Miyamoto
设计人： Koushirou Adachi , Katsuhiko Nishiwaki , Motoake Sakamoto , Tamotsu Tsukaguchi , Mitsuo Miyamoto

9. 外观设计

USD276550S Electric fan 失效
公开(公告)号：USD276550S
公开(公告)日：1984-11-27
申请号：US378799
申请日：1982-05-17
申请人： Shuichi Kouno , Katsuhiko Nishiwaki , Kenichi Watanabe
设计人： Shuichi Kouno , Katsuhiko Nishiwaki , Kenichi Watanabe

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式