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1. 发明授权

US6110833A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6110833A
公开(公告)日：2000-08-29
申请号：US33836
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： A61K38/00 , A61K38/30 , H01L21/8247 , H01L21/70
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译：提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙第二存储单元。此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

2. 发明授权

US6043120A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6043120A
公开(公告)日：2000-03-28
申请号：US33723
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate. A masking layer is deposited or grown on the poly I layer, and at least a portion of the masking layer is etched so as to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. An interpoly dielectric layer and a second polysilicon (poly II) layer is formed over the poly I layer and insulator substantially free of abrupt changes in step height.
摘要翻译：一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。在多晶硅层上沉积或生长掩模层，并且蚀刻掩模层的至少一部分，以便对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极电隔离。在多层I层和绝缘体上形成多层介电层和第二多晶硅（poly II）层，绝缘体基本上没有台阶高度的突然变化。

3. 发明授权

US06455888B1 Memory cell structure for elimination of oxynitride (ONO) etch residue and polysilicon stringers 有权
标题翻译：用于消除氧氮化物（ONO）蚀刻残留物和多晶硅桁架的记忆单元结构
公开(公告)号：US06455888B1
公开(公告)日：2002-09-24
申请号：US09506298
申请日：2000-02-17
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan
IPC分类号： H01L29788
CPC分类号： H01L27/11521 , A61K38/30
摘要： A method for fabricating a first memory cell and a second memory cell electrically isolated from each other is provided. A first polysilicon (poly I) layer is formed on an oxide coated substrate. Then, a sacrificial oxide layer and nitride layer are formed for masking the poly I layer. At least a portion of the masking layer is etched to pattern the first memory cell and the second memory cell and an unmasked portion therebetween. The unmasked portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator separates a floating gate of the first memory cell from a floating gate of the second memory cell. The insulator is etched so as to form a gap having gradually sloping sidewalls between a floating gate of the first memory cell and a floating gate of the second memory cell, the gap isolating the floating gate of the first memory cell from the floating gate of the second memory cell. Thereafter, an interpoly dielectric layer and a second polysilicon (poly II) layer are formed substantially free of abrupt changes in step height.
摘要翻译：提供了一种用于制造彼此电隔离的第一存储单元和第二存储单元的方法。在氧化物涂覆的基底上形成第一多晶硅（poly I）层。然后，形成用于掩蔽多晶硅层的牺牲氧化物层和氮化物层。蚀刻掩模层的至少一部分以对第一存储单元和第二存储单元进行图案化，并且在其间形成未屏蔽部分。多层I层的未屏蔽部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮置栅极与第二存储单元的浮置栅极分开。绝缘体被蚀刻以形成在第一存储单元的浮动栅极和第二存储单元的浮置栅极之间具有逐渐倾斜的侧壁的间隙，将第一存储单元的浮置栅极与第一存储单元的浮动栅极隔离的间隙第二存储单元。此后，形成基本上不具有台阶高度突然变化的互聚电介质层和第二多晶硅（poly II）层。

4. 发明授权

US6030868A Elimination of oxynitride (ONO) etch residue and polysilicon stringers through isolation of floating gates on adjacent bitlines by polysilicon oxidation 失效
标题翻译：通过多晶硅氧化隔离相邻位线上的浮栅，消除氧氮化物（ONO）蚀刻残渣和多晶硅桁架
公开(公告)号：US6030868A
公开(公告)日：2000-02-29
申请号：US33916
申请日：1998-03-03
申请人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
发明人： Kathleen R. Early , Michael K. Templeton , Nicholas H. Tripsas , Maria C. Chan , Mark T. Ramsbey
IPC分类号： H01L21/8247 , H01L27/115 , H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： A method for fabricating a first memory cell and a second memory cell having floating gates electrically isolated from each other. A first polysilicon (poly I) layer is formed on an oxide coated substrate, portions of the poly I layer to serve as future floating gates for the first and second memory cells. An interpoly dielectric layer is formed over the poly I layer. At least a portion of the interpoly dielectric layer is etched to expose at least a portion of the poly I layer so as to pattern the floating gates on either side of the exposed portion of the poly I layer. The exposed portion of the poly I layer is transformed into an insulator via thermal oxidation such that the insulator electrically isolates a floating gate of the first memory cell from a floating gate of the second memory cell. A second polysilicon (poly II) layer is formed substantially free of abrupt changes in step height.
摘要翻译：一种制造第一存储单元的方法和具有彼此电隔离的浮动栅极的第二存储单元。在氧化物涂覆的基底上形成第一多晶硅（poly I）层，多晶硅层的部分用作第一和第二存储单元的未来浮动栅极。在多晶硅层上形成多层介电层。蚀刻至少一部分互电介质层以暴露多晶硅层的至少一部分，以便在多晶硅层的暴露部分的任一侧上对浮动栅极进行图案化。多层I的暴露部分通过热氧化转变为绝缘体，使得绝缘体将第一存储器单元的浮动栅极与第二存储单元的浮置栅极电隔离。形成基本上没有台阶高度突然变化的第二多晶硅（poly II）层。

5. 发明授权

US06420702B1 Non-charging critical dimension SEM metrology standard 失效
标题翻译：非充电临界尺寸SEM测量标准
公开(公告)号：US06420702B1
公开(公告)日：2002-07-16
申请号：US09611641
申请日：2000-07-07
申请人： Nicholas H. Tripsas , Bhanwar Singh , Michael K. Templeton
发明人： Nicholas H. Tripsas , Bhanwar Singh , Michael K. Templeton
IPC分类号： H01J3728
CPC分类号： H01J37/28 , G01B15/00 , H01J2237/2814
摘要： An SEM measurement standard for measuring linewidths of 0.1 microns and below utilizes two different conducting materials in order to prevent charging effects. The top material is selected to use grain morphology to focus secondary electrons, and to obtain improved image contrast. The inventive standard is comprised of materials which are commonly used in semiconductor manufacturing and which do not cause contamination of fabrication facilities.
摘要翻译：用于测量0.1微米及以下线宽的SEM测量标准使用两种不同的导电材料，以防止充电效应。选择顶部材料以使用晶粒形态来聚焦二次电子，并获得改善的图像对比度。本发明的标准由通常用于半导体制造并且不会引起制造设备污染的材料组成。

6. 发明授权

US06291137B1 Sidewall formation for sidewall patterning of sub 100 nm structures 失效
标题翻译：侧壁形成用于侧向图案化的亚100nm结构
公开(公告)号：US06291137B1
公开(公告)日：2001-09-18
申请号：US09234380
申请日：1999-01-20
申请人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
发明人： Christopher F. Lyons , Michael K. Templeton , Kathleen R. Early
IPC分类号： G03C500
CPC分类号： H01L21/76885 , H01L21/28132 , H01L21/32136 , H01L21/32137 , H01L21/32139
摘要： In one embodiment, the present invention relates to a method of forming a conductive structure having a width of about 100 nm or less, involving the steps of providing a substrate having a conductive film; patterning a sidewall template over a first portion of the conductive film wherein a second portion of the conductive film is exposed, the sidewall template having at least one sidewall over the conductive film; depositing a sidewall film over the conductive film and the sidewall template, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template and a horizontal portion in areas not adjacent the sidewall of the sidewall template; removing the horizontal portion of the sidewall film exposing a third portion of the conductive film; removing the sidewall template exposing a fourth portion of the conductive film; and etching the third portion and the fourth portion of the conductive film thereby providing the conductive structure having a width of about 100 nm or less underlying the vertical portion of the sidewall film.
摘要翻译：在一个实施例中，本发明涉及一种形成宽度为约100nm或更小的导电结构的方法，包括提供具有导电膜的基板的步骤; 在所述导电膜的第一部分上图案化侧壁模板，其中所述导电膜的第二部分被暴露，所述侧壁模板在所述导电膜上具有至少一个侧壁; 在所述导电膜和所述侧壁模板上沉积侧壁膜，所述侧壁膜具有邻近所述侧壁模板的侧壁的垂直部分和在不邻近所述侧壁模板的侧壁的区域中的水平部分; 去除暴露导电膜的第三部分的侧壁膜的水平部分; 去除暴露导电膜的第四部分的侧壁模板; 并且蚀刻导电膜的第三部分和第四部分，从而提供具有约100nm或更小的宽度在该侧壁膜的垂直部分下方的导电结构。

7. 发明授权

US06269322B1 System and method for wafer alignment which mitigates effects of reticle rotation and magnification on overlay 有权
标题翻译：用于晶片对准的系统和方法，其减轻掩模旋转和放大对覆盖物的影响
公开(公告)号：US06269322B1
公开(公告)日：2001-07-31
申请号：US09266361
申请日：1999-03-11
申请人： Michael K. Templeton , Bharath Rangarajan , Kathleen R. Early , Terry Manchester
发明人： Michael K. Templeton , Bharath Rangarajan , Kathleen R. Early , Terry Manchester
IPC分类号： G03B2742
CPC分类号： G03F9/70
摘要： The present invention relates to wafer alignment. A reticle is employed which includes, a design and first and second alignment marks. The second alignment mark is symmetric to the first alignment mark such that a reticle center point is a midpoint of the first and second alignment marks. The first alignment mark is printed on a surface layer of the wafer. The second alignment mark is printed on the surface layer at an offset from the first alignment mark. A virtual alignment mark is determined, the virtual alignment mark being a midpoint of the printed first and second alignment marks. The virtual alignment mark is employed to facilitate aligning the wafer. The symmetric relationship between the first and second alignment mark results in the negation of print errors of the marks due to reticle rotation and/or lens magnification with respect to the virtual alignment mark. The employment of the virtual alignment mark in wafer alignment substantially facilitates mitigation of overlay error.
摘要翻译：本发明涉及晶圆对准。使用掩模版，其包括设计和第一和第二对准标记。第二对准标记与第一对准标记对称，使得标线片中心点是第一和第二对准标记的中点。将第一对准标记印刷在晶片的表面层上。第二对准标记以与第一对准标记偏移的方式印刷在表面层上。确定虚拟对准标记，虚拟对准标记是打印的第一和第二对准标记的中点。采用虚拟对准标记以便于对准晶片。第一和第二对准标记之间的对称关系导致相对于虚拟对准标记由于标线旋转和/或透镜放大而导致的标记的打印错误的否定。在晶片对准中使用虚拟对准标记基本上有助于减轻重叠误差。

8. 发明授权

US06534243B1 Chemical feature doubling process 有权
标题翻译：化学特征加倍工艺
公开(公告)号：US06534243B1
公开(公告)日：2003-03-18
申请号：US10000493
申请日：2001-10-23
申请人： Michael K. Templeton , Ramkumar Subramanian , Bharath Rangarajan , Kathleen R. Early , Ursula Q. Quinto
发明人： Michael K. Templeton , Ramkumar Subramanian , Bharath Rangarajan , Kathleen R. Early , Ursula Q. Quinto
IPC分类号： G03F7039
CPC分类号： G03F7/405 , G03F7/0035 , G03F7/40
摘要： In one embodiment, the present invention relates to a method of treating a patterned resist involving providing the patterned resist having a first number of structural features, the patterned resist comprising an acid catalyzed polymer; contacting a coating containing a coating material, at least one basic compound, a photoacid generator, and a dye with the patterned resist; irradiating the coated patterned resist; permitting a deprotection region to form within an inner portion of the patterned resist; and removing the coating and the deprotection region to provide a second number of patterned resist structural features, wherein the first number is smaller than the second number.
摘要翻译：在一个实施方案中，本发明涉及一种处理图案化抗蚀剂的方法，包括提供具有第一数目的结构特征的图案化抗蚀剂，所述图案化抗蚀剂包含酸催化聚合物; 使含有涂层材料的涂层，至少一种碱性化合物，光致酸发生剂和染料与图案化的抗蚀剂接触; 照射经涂覆的图案化抗蚀剂; 允许在图案化抗蚀剂的内部部分内形成去保护区; 并且去除涂层和去保护区域以提供第二数量的图案化抗蚀剂结构特征，其中第一数目小于第二数量。

9. 发明授权

US06316804B1 Oxygen implant self-aligned, floating gate and isolation structure 失效
标题翻译：氧气注入自对准，浮动门和隔离结构
公开(公告)号：US06316804B1
公开(公告)日：2001-11-13
申请号：US09569721
申请日：2000-05-11
申请人： Michael K. Templeton , Kathleen R. Early
发明人： Michael K. Templeton , Kathleen R. Early
IPC分类号： H01L29788
CPC分类号： H01L27/11521
摘要： A semiconductor apparatus and fabrication method for forming oxide isolation regions in a semiconductor substrate for use in forming self-aligned, floating gate MOS structures or other semiconductor devices. The method includes providing a semiconductor substrate member prefabricated having a barrier oxide layer, a polysilicon layer and a plurality of spaced apart silicon nitride layer portions fabricated on the polysilicon layer. The nitride layer portions delineate regions for forming the self-aligned floating gate MOS structures, as well as delineating portions of the silicon dioxide layer and portions of said polysilicon layer that are unprotected by the plurality of silicon nitride layer portions. The method further includes the step of implanting oxygen O2 ions into regions of the substrate, including those unprotected portions of the silicon dioxide layer and portions of the polysilicon layer to form the oxide isolation regions. After removing the silicon nitride layer portions, and exposing the polysilicon layer portions, the implanted structure is annealed and made ready for forming the self-aligned floating gate MOS structures, or other semiconductor structure on the conductive material pads. The floating gates may be formed having a minimal width with respect to an underlying active region.
摘要翻译：一种半导体装置和制造方法，用于在用于形成自对准的浮置栅极MOS结构或其它半导体器件的半导体衬底中形成氧化物隔离区。该方法包括提供预制的半导体衬底构件，其具有制造在多晶硅层上的阻挡氧化物层，多晶硅层和多个间隔开的氮化硅层部分。氮化物层部分描绘用于形成自对准浮置栅极MOS结构的区域，以及描绘未被多个氮化硅层部分保护的二氧化硅层的部分和所述多晶硅层的部分。该方法还包括将氧O 2离子注入到衬底的区域中的步骤，包括二氧化硅层的那些未受保护的部分和多晶硅层的部分以形成氧化物隔离区。在去除氮化硅层部分并暴露多晶硅层部分之后，将注入结构退火并准备好在导电材料焊盘上形成自对准浮栅MOS结构或其它半导体结构。浮动栅极可以形成为相对于下面的有源区域具有最小宽度。

10. 发明授权

US06197455B1 Lithographic mask repair using a scanning tunneling microscope 失效
标题翻译：使用扫描隧道显微镜进行平版印刷修复
公开(公告)号：US06197455B1
公开(公告)日：2001-03-06
申请号：US09231679
申请日：1999-01-14
申请人： Sanjay K. Yedur , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Kathleen R. Early
发明人： Sanjay K. Yedur , Bharath Rangarajan , Bhanwar Singh , Michael K. Templeton , Kathleen R. Early
IPC分类号： G03F900
CPC分类号： G03F1/74 , Y10S977/856 , Y10S977/859
摘要： A method of repairing defects in a photomask used in the formation of a semiconductor wafer includes the use of a scanning tunneling microscope. The scanning tunneling microscope includes a very sharp tip having a diameter on the order of 100 Å or less. In order to remove excess material from a mask layer in the photomask, the tip is placed into contact with those regions having such excess material and the tip is used to scrape the excess material away. In order to add material to voids in a mask layer of the photomask, the tip is placed in proximity to those areas in need of the excess material and caused to deposit such material upon, for example, application of a bias voltage to the tip.
摘要翻译：修复用于形成半导体晶片的光掩模中的缺陷的方法包括使用扫描隧道显微镜。扫描隧道显微镜包括具有大约等于或小于100埃的直径的非常锋利的尖端。为了从光掩模中的掩模层去除多余的材料，将尖端放置成与具有这种多余材料的那些区域接触，并且尖端用于刮除多余的材料。为了向光掩模的掩模层中的空隙添加材料，将尖端放置在需要多余材料的那些区域附近，并且使得将这种材料沉积在例如向尖端施加偏置电压。

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