专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10211219B2 Nonvolatile semiconductor memory device and manufacturing method thereof 有权
公开(公告)号：US10211219B2
公开(公告)日：2019-02-19
申请号：US15666653
申请日：2017-08-02
申请人： Kabushiki Kaisha Toshiba
发明人： Masaru Kito , Hideaki Aochi , Ryota Katsumata , Akihiro Nitayama , Masaru Kidoh , Hiroyasu Tanaka , Yoshiaki Fukuzumi , Yasuyuki Matsuoka , Mitsuru Sato
IPC分类号： H01L27/32 , H01L27/11582 , H01L21/822 , H01L27/06 , H01L27/105 , H01L27/115 , H01L27/11573 , H01L27/11578 , H01L27/11556 , G11C16/04
摘要： A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

2. 发明授权

US09437656B2 Semiconductor memory device 有权
公开(公告)号：US09437656B2
公开(公告)日：2016-09-06
申请号：US14515205
申请日：2014-10-15
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L27/24 , G11C13/00 , G11C16/04 , H01L23/525 , H01L23/528
CPC分类号： H01L27/2463 , G11C13/0007 , G11C16/04 , G11C2213/73 , H01L23/525 , H01L23/528 , H01L27/2436 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor memory device according to one embodiment of the present invention includes a dielectric film configured to store information depending on presence or absence of a conductive path therein, and a plurality of electrodes provided to contact a first surface of the dielectric film. The conductive path can be formed between two electrodes arbitrarily selected form the plurality of electrodes. The conductive path has a rectifying property of allowing a current to flow more easily in a first direction connecting arbitrary two electrodes than in a second direction opposite to the first direction. The largest possible number of the conductive paths that may be formed is larger than the number of the plurality of electrodes.

3. 发明授权

US09312134B2 Nonvolatile semiconductor memory device and method for manufacturing same 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US09312134B2
公开(公告)日：2016-04-12
申请号：US14150504
申请日：2014-01-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L29/792 , H01L21/223 , H01L27/115 , H01L29/66 , H01L21/265 , H01L29/78
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于第一方向第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

4. 发明授权

US09153340B2 Magnetic storage element, magnetic storage device, magnetic memory, and driving method 有权
标题翻译：磁存储元件，磁存储器，磁存储器和驱动方法
公开(公告)号：US09153340B2
公开(公告)日：2015-10-06
申请号：US14081149
申请日：2013-11-15
申请人： Kabushiki Kaisha Toshiba
发明人： Hirofumi Morise , Yoshiaki Fukuzumi , Tsuyoshi Kondo , Shiho Nakamura , Hideaki Aochi
IPC分类号： G11C11/00 , G11C19/02 , G11C19/08 , H01L27/22 , H01L43/08
CPC分类号： G11C19/02 , G11C19/08 , H01L27/22 , H01L43/08
摘要： A magnetic storage element includes a magnetic nanowire. A cross-section of the magnetic nanowire has first and second visible outlines, the first visible outline has a first minimal point at which a distance from a virtual straight line becomes minimal, a second minimal point at which the distance from the virtual straight line becomes minimal, and a first maximal point at which the distance from the virtual straight line becomes longest between the first minimal point and the second minimal point, and an angle between a first straight line connecting the first minimal point and the second minimal point, and one of a second straight line connecting the first minimal point and the first maximal point and a third straight line connecting the second minimal point and the first maximal point is not smaller than four degrees and not larger than 30 degrees.
摘要翻译：磁存储元件包括磁性纳米线。磁纳米线的横截面具有第一和第二可视轮廓，第一可见轮廓具有从虚拟直线的距离变得最小的第一最小点，距离虚拟直线的距离变成第二最小点最小和第一最大点，在该第一最大点处，从虚拟直线到第一最小点和第二最小点之间的距离变得最长，以及连接第一最小点和第二最小点的第一直线之间的角度，以及一个连接第一最小点和第一最大点的第二直线和连接第二最小点和第一最大点的第三直线不小于四度且不大于30度。

5. 发明授权

US09142759B2 Magnetic memory device and method of magnetic domain wall motion 有权
标题翻译：磁存储器件及磁畴壁运动方法
公开(公告)号：US09142759B2
公开(公告)日：2015-09-22
申请号：US14310152
申请日：2014-06-20
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Hirofumi Morise , Hideaki Fukuzawa , Akira Kikitsu , Yoshiaki Fukuzumi
IPC分类号： G11C11/15 , H01L43/08 , G11C11/16 , H01L27/22 , H01L41/09 , H01L41/12 , H01L43/10 , H01F10/32
CPC分类号： H01L43/08 , G11C11/16 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C11/1693 , H01F10/3236 , H01F10/325 , H01F10/3254 , H01F10/3286 , H01F10/3295 , H01L27/228 , H01L41/0986 , H01L41/12 , H01L43/10
摘要： A magnetic memory device comprises a first electrode, a second electrode, a laminated structure comprising plural first magnetic layers being provided between the first electrode and the second electrode, a second magnetic layer comprising different composition elements from that of the first magnetic layer and being provided between plural first magnetic layers, a piezoelectric body provided on a opposite side to a side where the first electrode is provided in the laminated structure, and a third electrode applying voltage to the piezoelectric body and provided on a different position from a position where the first electrode is provided in the piezoelectric body.
摘要翻译：磁存储器件包括第一电极，第二电极，层叠结构，其包括设置在第一电极和第二电极之间的多个第一磁性层，第二磁性层包括与第一磁性层不同的组成元素，在多个第一磁性层之间，在层压结构中设置在与设置有第一电极的一侧相反的一侧的压电体，以及将第三电极向压电体施加电压，并且设置在与第一电极的位置不同的位置，电极设置在压电体中。

6. 发明申请

US20150102399A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20150102399A1
公开(公告)日：2015-04-16
申请号：US14491385
申请日：2014-09-19
申请人： Kabushiki Kaisha Toshiba
发明人： Haruka Sakuma , Shuichi Toriyama , Masumi Saitoh , Yoshiaki Fukuzumi , Naoki Yasuda
IPC分类号： H01L27/115
CPC分类号： H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A memory string includes: a first semiconductor layer formed in a columnar shape extending in a stacking direction perpendicular to a substrate; a tunnel insulating film formed surrounding a side surface of the first semiconductor layer; a charge accumulation film formed surrounding the tunnel insulating film and configured to be capable of accumulating charges; a block insulating film formed surrounding the charge accumulation film; and a plurality of first conductive layers formed surrounding the block insulating film and disposed at a predetermined interval in the stacking direction. The first semiconductor layer comprises carbon-doped silicon and being formed to have different carbon concentrations in upper and lower portions in the stacking direction.
摘要翻译：存储器串包括：第一半导体层，其形成为在垂直于衬底的层叠方向上延伸的柱状; 形成在所述第一半导体层的侧面周围的隧道绝缘膜; 形成在隧道绝缘膜周围的电荷蓄积膜，其能够积累电荷; 形成在电荷累积膜周围的块绝缘膜; 以及多个第一导电层，其形成为围绕所述块绝缘膜并且以堆叠方向以预定间隔设置。第一半导体层包括碳掺杂硅并且被形成为在堆叠方向上的上部和下部具有不同的碳浓度。

7. 发明申请

US20140252443A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20140252443A1
公开(公告)日：2014-09-11
申请号：US14018543
申请日：2013-09-05
申请人： Kabushiki Kaisha Toshiba
发明人： Tomoya KAWAI , Jun Fujiki , Yoshiaki Fukuzumi , Hideaki Aochi
IPC分类号： H01L29/78
CPC分类号： H01L27/11578 , H01L27/1157 , H01L27/11582
摘要： According to one embodiment, a nonvolatile semiconductor memory device comprises a semiconductor substrate, a first layer formed above the semiconductor substrate, a first conductive layer, an inter-electrode insulating layer, and a second conductive layer sequentially stacked above the first layer, a memory film formed on an inner surface of each of a pair of through holes provided in the first conductive layer, the inter-electrode insulating layer, and the second conductive layer and extending in a stacking direction, a semiconductor layer formed on the memory film in the pair of through holes, and a metal layer formed in part of the pair of through holes and/or in part of a connection hole that is provided in the first layer and connects lower end portions of the pair of through holes, the metal layer being in contact with the semiconductor layer.
摘要翻译：根据一个实施例，非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一层，第一导电层，电极间绝缘层和顺序堆叠在第一层之上的第二导电层，存储器形成在设置在第一导电层，电极间绝缘层和第二导电层中并在层叠方向上延伸的一对通孔的内表面上的膜，形成在存储膜中的半导体层一对通孔和形成在一对通孔的一部分中的金属层和/或连接孔的一部分中的金属层，该连接孔设置在第一层中并连接该对通孔的下端部，金属层为与半导体层接触。

8. 发明申请

US20140117434A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20140117434A1
公开(公告)日：2014-05-01
申请号：US14150504
申请日：2014-01-08
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kito , Masaru Kidoh , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Junya Matsunami , Tomoko Fujiwara , Hideaki Aochi , Ryouhei Kirisawa , Yoshimasa Mikajiri , Shigeto Oota
IPC分类号： H01L27/115 , H01L21/265 , H01L29/66 , H01L21/223 , H01L29/78 , H01L29/792
CPC分类号： H01L27/11582 , H01L21/223 , H01L21/265 , H01L27/11578 , H01L29/04 , H01L29/1037 , H01L29/16 , H01L29/42344 , H01L29/4916 , H01L29/66666 , H01L29/66833 , H01L29/7827 , H01L29/792 , H01L29/7926
摘要： A nonvolatile semiconductor memory device, includes: a stacked structural unit including a plurality of insulating films alternately stacked with a plurality of electrode films in a first direction; a selection gate electrode stacked on the stacked structural unit in the first direction; an insulating layer stacked on the selection gate electrode in the first direction; a first semiconductor pillar piercing the stacked structural unit, the selection gate electrode, and the insulating layer in the first direction, a first cross section of the first semiconductor pillar having an annular configuration, the first cross section being cut in a plane orthogonal to the first direction; a first core unit buried in an inner side of the first semiconductor pillar, the first core unit being recessed from an upper face of the insulating layer; and a first conducting layer of the first semiconductor pillar provided on the first core unit to contact the first core unit.
摘要翻译：一种非易失性半导体存储器件，包括：堆叠结构单元，包括在第一方向上交替地堆叠有多个电极膜的多个绝缘膜; 选择栅极电极，其沿所述第一方向堆叠在所述层叠结构单元上; 绝缘层，其沿所述第一方向堆叠在所述选择栅电极上; 第一半导体柱在第一方向上穿透层叠结构单元，选择栅电极和绝缘层，第一半导体柱的第一截面具有环形构造，第一横截面在垂直于第一方向第一核心单元，其被埋在第一半导体柱的内侧，第一芯单元从绝缘层的上表面凹入; 以及设置在所述第一芯单元上以接触所述第一芯单元的所述第一半导体柱的第一导电层。

9. 发明申请

US20140080297A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20140080297A1
公开(公告)日：2014-03-20
申请号：US14090199
申请日：2013-11-26
申请人： Kabushiki Kaisha Toshiba
发明人： Ichiro Mizushima , Yoshiaki Fukuzumi , Shinji Mori
IPC分类号： H01L21/28 , H01L29/423
CPC分类号： H01L29/40117 , H01L27/11582 , H01L29/42352
摘要： According to one embodiment, a semiconductor device, including a substrate, a stacked layer body provided above the substrate, the stacked layer body alternately stacking an insulator and an electrode film one on another, silicon pillars contained with fluorine, the silicon pillar penetrating through and provided in the stacked layer body, a tunnel insulator provided on a surface of the silicon pillar facing to the stacked layer body, a charge storage layer provided on a surface of the tunnel insulator facing to the stacked layer body, a block insulator provided on a surface of the charge storage layer facing to the stacked layer body, the block insulator being in contact with the electrode film, and an embedded portion provided in the silicon pillars.
摘要翻译：根据一个实施例，一种半导体器件，包括衬底，在衬底上方设置的层叠体，堆叠层体彼此交替堆叠绝缘体和电极膜，含有氟的硅柱，穿透硅柱的硅柱，设置在堆叠层体上的隧道绝缘体，设置在与层叠体主体相对的硅柱的表面上的隧道绝缘体，设置在隧道绝缘体的面向堆叠层主体的表面上的电荷存储层，面向堆叠层体的电荷存储层的表面，块绝缘体与电极膜接触，以及设置在硅柱中的嵌入部。

10. 发明授权

US09741738B2 Non-volatile semiconductor storage device and method of manufacturing the same 有权
公开(公告)号：US09741738B2
公开(公告)日：2017-08-22
申请号：US15141135
申请日：2016-04-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoshiaki Fukuzumi , Ryota Katsumata , Masaru Kidoh , Masaru Kito , Hiroyasu Tanaka , Yosuke Komori , Megumi Ishiduki , Hideaki Aochi
IPC分类号： H01L29/51 , H01L27/11 , H01L27/11582 , G11C16/04 , H01L27/11556 , H01L27/11573 , H01L27/11578 , H01L27/105 , H01L27/11575 , H01L27/11551
CPC分类号： H01L27/11582 , G11C16/0483 , H01L27/1052 , H01L27/11551 , H01L27/11556 , H01L27/11573 , H01L27/11575 , H01L27/11578 , H01L29/513
摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式