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1. 发明授权

US06323098B1 Manufacturing method of a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06323098B1
公开(公告)日：2001-11-27
申请号：US09261159
申请日：1999-03-03
申请人： Tamotsu Ogata , Junichi Tsuchimoto , Yutaka Inaba , Kiyoshi Mori
发明人： Tamotsu Ogata , Junichi Tsuchimoto , Yutaka Inaba , Kiyoshi Mori
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31662
摘要： After a bottom electrode 30 of a capacitor is formed, a nitride film as an insulating film 32 of the capacitor is formed on the bottom electrode 30 by CVD. Then, the insulating film 32 is wet-oxidized at a temperature in a range of 700° C. to 760° C. Finally, a top electrode 34 of the capacitor is formed on the insulating film 32. The insulating film 32 forming step includes a substep of increasing the temperature of a silicon wafer to a CVD reaction temperature in an ammonia atmosphere.
摘要翻译：在形成电容器的底部电极30之后，通过CVD在底部电极30上形成作为电容器的绝缘膜32的氮化物膜。然后，绝缘膜32在700℃至760℃的温度范围内进行湿式氧化。最后，在绝缘膜32上形成电容器的顶部电极34.绝缘膜32形成步骤包括在氨气氛中将硅晶片的温度升高到CVD反应温度的子步骤。

2. 发明授权

US6159785A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US6159785A
公开(公告)日：2000-12-12
申请号：US201832
申请日：1998-12-01
申请人： Junichi Tsuchimoto , Yutaka Inaba , Tamotsu Ogata , Kiyoshi Mori
发明人： Junichi Tsuchimoto , Yutaka Inaba , Tamotsu Ogata , Kiyoshi Mori
IPC分类号： H01L27/108 , H01L21/02 , H01L21/20 , H01L21/8242 , H10L21/8234
CPC分类号： H01L28/84 , H01L21/02532 , H01L21/02667 , H01L21/2022 , H01L27/10852
摘要： An amorphous silicon film is formed on an interlayer insulating film to cover an upper surface of the interlayer insulating film, and a side surface and a bottom surface of an opening formed at the interlayer insulating film. Phosphorus ions are implanted into the amorphous silicon film. The phosphorous ions are implanted into the amorphous silicon film located on the upper surface of the interlayer insulating film to prevent crystal grains from growing, and thus a polysilicon film having no hemispherical grains is formed. Accordingly, a semiconductor device having capacitors with respective storage nodes adjacent to each other that are electrically isolated properly is obtained.
摘要翻译：在层间绝缘膜上形成非晶硅膜以覆盖层间绝缘膜的上表面，以及形成在层间绝缘膜上的开口的侧表面和底表面。将磷离子注入到非晶硅膜中。将磷离子注入到位于层间绝缘膜的上表面的非晶硅膜中，以防止晶粒生长，从而形成不具有半球状晶粒的多晶硅膜。因此，获得具有彼此相邻的具有彼此电隔离的各个存储节点的电容器的半导体器件。

3. 发明授权

US06207527B1 Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06207527B1
公开(公告)日：2001-03-27
申请号：US09335690
申请日：1999-06-18
申请人： Kiyoshi Mori , Junichi Tsuchimoto , Yutaka Inaba , Tamotsu Ogata
发明人： Kiyoshi Mori , Junichi Tsuchimoto , Yutaka Inaba , Tamotsu Ogata
IPC分类号： H01L2120
CPC分类号： H01L28/82 , H01L28/84 , H01L28/90
摘要： A method of manufacturing a semiconductor device including a capacitor having an increased capacity with improved yield is provided. Ions are implanted at an incidence angle of 0° in a dose of 8×1015atom/cm2, at an energy of 20 keV, using a heavy current device and an amorphous silicon film having an upper surface flattened is formed. Only the flattened amorphous silicon film formed on the upper surface of an interlayer oxide film is etched back to form a storage electrode.
摘要翻译：提供一种制造半导体器件的方法，该半导体器件包括具有增加的容量并且具有提高的产量的电容器。使用大电流器件，以20keV的能量以8×10 15原子/ cm 2的剂量以0°的入射角植入离子，形成具有上表面变平的非晶硅膜。只有形成在层间氧化膜的上表面上的扁平状非晶硅膜被回蚀以形成存储电极。

4. 发明授权

US06599795B2 Method of manufacturing semiconductor device including a step of forming a silicide layer, and semiconductor device manufactured thereby 失效
公开(公告)号：US06599795B2
公开(公告)日：2003-07-29
申请号：US09775713
申请日：2001-02-05
申请人： Tamotsu Ogata
发明人： Tamotsu Ogata
IPC分类号： H01L218242
CPC分类号： H01L27/10894 , H01L21/76897 , H01L21/823418 , H01L27/10873
摘要： A gate insulating film 2 is formed on a DRAM circuit region 11 and a logic circuit region 12 of a semiconductor substrate, and gate electrodes 3 are formed on the gate insulating film 2. Sidewalls of the gate electrodes 3 are oxidized. A first insulating film 4 is formed all over the semiconductor substrate 1. A sidewall insulating film 41 made of a first insulating film 4 is leaved on the both sides of the gate electrodes 3. A diffusion layer 5 is formed in the semiconductor substrate 1 by implanting ions with the first insulating film 4 and the sidewall insulating film 41 as a mask. A protection film 6 is formed on the first insulating film 4 in the DRAM circuit region 11 and on the logic circuit region 12 except for specific regions 51 of the diffusion layer 5 around certain gate electrodes 3a. A silicide layer 7 is formed in an upper layer portion of the diffusion layer 5 by a salicide technique. The protection film 6 is removed by wet etching from the DRAM circuit region 11, and massive residues 71 left behind on the protection film 6 are lifted off for removal.

5. 发明授权

US06593179B2 Method of manufacturing a semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06593179B2
公开(公告)日：2003-07-15
申请号：US09553331
申请日：2000-04-20
申请人： Tamotsu Ogata
发明人： Tamotsu Ogata
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L21/31111 , H01L21/3144 , H01L21/84 , H01L27/0688 , H01L27/1203 , H01L28/40
摘要： An isolation oxide film is formed on a silicon substrate, and a pad oxide film is formed in an active region. A lower electrode of a capacitor is formed on the isolation oxide film, and a multilayered film (ON film) comprising a silicon oxide film and a silicon nitride film is formed on the lower electrode. A mask oxide film is formed on the ON film so as to cover only the area in the vicinity of the lower electrode. The ON film is patterned by means of wet etching capable of selectively removing the silicon nitride film. The pad oxide film and the mask oxide film are removed before forming a gate oxide film. Fabrication of a capacitor and a transistor is completed by formation of gate electrodes and an upper electrode.
摘要翻译：在硅衬底上形成隔离氧化膜，在有源区形成衬垫氧化膜。在隔离氧化膜上形成电容器的下电极，在下电极上形成由氧化硅膜和氮化硅膜构成的多层膜（导电膜）。在ON膜上形成掩模氧化膜，仅覆盖下电极附近的区域。通过能够选择性地去除氮化硅膜的湿蚀刻来对ON膜进行图案化。在形成栅极氧化膜之前去除衬垫氧化物膜和掩模氧化物膜。通过形成栅电极和上电极来完成电容器和晶体管的制造。

6. 发明授权

US08779593B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US08779593B2
公开(公告)日：2014-07-15
申请号：US13592540
申请日：2012-08-23
申请人： Tamotsu Ogata
发明人： Tamotsu Ogata
IPC分类号： H01L29/40 , H01L23/52 , H01L23/48
CPC分类号： H01L23/522 , H01L23/5223 , H01L23/5286 , H01L23/53238 , H01L23/53295 , H01L24/05 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05006 , H01L2224/05147 , H01L2224/05553 , H01L2224/05558 , H01L2224/05624 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/10161 , H01L2924/10253 , H01L2924/12042 , H01L2924/1306 , H01L2924/13091 , H01L2924/15788 , H01L2924/181 , H01L2924/30107 , H01L2924/00014 , H01L2924/00
摘要： Also in a semiconductor integrated circuit device including a copper embedded wiring as a main wiring layer, generally, the uppermost-layer wiring layer is often an aluminum-based pad layer in order to ensure wire bonding characteristics. The aluminum-based pad layer is also generally used as a wiring layer (general intercoupling wiring such as power source wiring or signal wiring). However, such a general intercoupling wiring has a relatively large wiring length. This causes a demerit for the device to be susceptible to damages during a plasma treatment due to the antenna effect, and other demerits. With the present invention, in a semiconductor integrated circuit device including a metal multilayer wiring system having a lower-layer embedded type multilayer wiring layer and an upper-layer non-embedded type aluminum-based pad metal layer, the non-embedded type aluminum-based pad metal layer substantially does not have a power supply ring wiring.
摘要翻译：同样在包括铜嵌入布线作为主布线层的半导体集成电路器件中，通常为了确保引线接合特性，最上层布线层通常是铝基焊盘层。铝基焊盘层也通常用作布线层（一般的互耦合布线，例如电源布线或信号布线）。然而，这种一般的互相布线具有相对较大的布线长度。这导致器件在等离子体处理期间由于天线效应以及其他缺点而容易受到损坏。通过本发明，在包括具有下层嵌入式多层布线层和上层非嵌入式铝基焊盘金属层的金属多层布线系统的半导体集成电路装置中，非嵌入式铝 - 基底垫金属层基本上不具有电源环布线。

7. 发明授权

US06215146B1 Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06215146B1
公开(公告)日：2001-04-10
申请号：US09090420
申请日：1998-06-04
申请人： Hiroshi Umeda , Tamotsu Ogata , Hiroshi Kurokawa , Hiroaki Tamura
发明人： Hiroshi Umeda , Tamotsu Ogata , Hiroshi Kurokawa , Hiroaki Tamura
IPC分类号： H01L29788
CPC分类号： H01L21/28202 , H01L29/518
摘要： An object is to provide a semiconductor device having high reliability and capable of high speed operation. The semiconductor device includes a silicon substrate, a silicon nitrided oxide film formed on the silicon substrate, and a gate electrode formed on the silicon nitrided oxide film. Nitrogen is distributed only in the vicinity of an interface between the silicon substrate and the silicon nitrided oxide film. In the vicinity of the interface, every nitrogen atom is bonded to two silicon atoms and one oxygen atom.
摘要翻译：本发明的目的是提供一种具有高可靠性且能够高速操作的半导体器件。半导体器件包括硅衬底，形成在硅衬底上的氮化氮化物膜和形成在硅氮化氧化物膜上的栅电极。氮仅分布在硅衬底和硅氮化氧化物膜之间的界面附近。在界面附近，每个氮原子与两个硅原子和一个氧原子键合。

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