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1. 发明申请

US20060208325A1 Semiconductor device with gate insulating film and manufacturing method thereof 审中-公开
标题翻译：具有栅极绝缘膜的半导体器件及其制造方法
公开(公告)号：US20060208325A1
公开(公告)日：2006-09-21
申请号：US11373112
申请日：2006-03-13
申请人： Masaharu Mizutani , Masao Inoue , Jiro Yugami , Junichi Tsuchimoto , Koji Nomura , Yasuhiro Shimamoto
发明人： Masaharu Mizutani , Masao Inoue , Jiro Yugami , Junichi Tsuchimoto , Koji Nomura , Yasuhiro Shimamoto
IPC分类号： H01L29/94
CPC分类号： H01L29/7833 , H01L29/1083 , H01L29/6659
摘要： A MISFET includes: a p type substrate having a channel region with an impurity concentration C; an insulating film made of SiO2 and formed on the channel region; and an insulating film made of HfSiON and formed on the gate insulating film. When there is a postulated MISFET including a postulated substrate having a channel region with the impurity concentration C and made of a material identical to the substrate and an insulating film made solely of SiON formed on the channel region, said impurity concentration C of channel region is set so that a maximum value of mobility of electrons in said channel region is higher than a maximum value of mobility of electrons in the postulated channel region. Thus, the power supply voltage can be reduced and the power consumption can be reduced.
摘要翻译： MISFET包括：具有杂质浓度C的沟道区的p型衬底; 形成在沟道区上的由SiO 2构成的绝缘膜; 以及由栅极绝缘膜形成的由HfSiON构成的绝缘膜。当存在假设的MISFET，其包括具有杂质浓度C并且由与衬底相同的材料制成的沟道区域和由沟道区域上形成的仅由SiON制成的绝缘膜的假定衬底时，沟道区的杂质浓度C 使得所述沟道区中的电子的迁移率的最大值高于假定沟道区中的电子的迁移率的最大值。因此，可以降低电源电压并且可以降低功耗。

2. 发明授权

US06809001B2 Semiconductor device and method for producing a semiconductor device 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06809001B2
公开(公告)日：2004-10-26
申请号：US09833734
申请日：2001-04-13
申请人： Masami Shirosaki , Junichi Tsuchimoto , Kiyoshi Mori
发明人： Masami Shirosaki , Junichi Tsuchimoto , Kiyoshi Mori
IPC分类号： H01L2120
CPC分类号： H01L27/10852 , H01L27/10817 , H01L27/10885 , H01L28/82 , H01L28/84 , H01L28/90
摘要： In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.
摘要翻译：在包括圆柱形存储节点的半导体器件中，通过仅通过热处理仅在圆柱形部分的外壁上形成无定形硅氧烷膜中的硅酮晶粒来增加存储节点的表面积，从而在外部形成粗糙表面并且将无定形硅氧烷膜留在内壁中，而不对内壁进行表面粗糙化处理，由此保持圆柱形部分的物理强度并且防止圆柱形部分的破坏和破裂。

3. 发明授权

US06323098B1 Manufacturing method of a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US06323098B1
公开(公告)日：2001-11-27
申请号：US09261159
申请日：1999-03-03
申请人： Tamotsu Ogata , Junichi Tsuchimoto , Yutaka Inaba , Kiyoshi Mori
发明人： Tamotsu Ogata , Junichi Tsuchimoto , Yutaka Inaba , Kiyoshi Mori
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/3144 , H01L21/31662
摘要： After a bottom electrode 30 of a capacitor is formed, a nitride film as an insulating film 32 of the capacitor is formed on the bottom electrode 30 by CVD. Then, the insulating film 32 is wet-oxidized at a temperature in a range of 700° C. to 760° C. Finally, a top electrode 34 of the capacitor is formed on the insulating film 32. The insulating film 32 forming step includes a substep of increasing the temperature of a silicon wafer to a CVD reaction temperature in an ammonia atmosphere.
摘要翻译：在形成电容器的底部电极30之后，通过CVD在底部电极30上形成作为电容器的绝缘膜32的氮化物膜。然后，绝缘膜32在700℃至760℃的温度范围内进行湿式氧化。最后，在绝缘膜32上形成电容器的顶部电极34.绝缘膜32形成步骤包括在氨气氛中将硅晶片的温度升高到CVD反应温度的子步骤。

4. 发明授权

US06232628B1 Semiconductor device having stacked capacitor structure 失效
标题翻译：具有层叠电容器结构的半导体器件
公开(公告)号：US06232628B1
公开(公告)日：2001-05-15
申请号：US09086752
申请日：1998-05-29
申请人： Masami Shirosaki , Junichi Tsuchimoto , Kiyoshi Mori
发明人： Masami Shirosaki , Junichi Tsuchimoto , Kiyoshi Mori
IPC分类号： H01L31119
CPC分类号： H01L27/10852 , H01L27/10817 , H01L27/10885 , H01L28/82 , H01L28/84 , H01L28/90
摘要： In a semiconductor device comprising a cylindrical storage node, the surface area of the storage node is increased by forming silicone grains in an amorphous silicone film by a heat treatment only to an outer wall of the cylindrical portion to thereby form a roughened surface in the outer wall, and the amorphous silicone film is left in an inner wall without conducting a surface roughening treatment to the inner wall whereby the physical strength of the cylindrical portion is maintained and the destruction and the breakage of the cylindrical portion are prevented.
摘要翻译：在包括圆柱形存储节点的半导体器件中，通过仅通过热处理仅在圆柱形部分的外壁上形成无定形硅氧烷膜中的硅酮晶粒来增加存储节点的表面积，从而在外部形成粗糙表面并且将无定形硅氧烷膜留在内壁中，而不对内壁进行表面粗糙化处理，由此保持圆柱形部分的物理强度并且防止圆柱形部分的破坏和破裂。

5. 发明授权

US6159785A Semiconductor device and manufacturing method thereof 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US6159785A
公开(公告)日：2000-12-12
申请号：US201832
申请日：1998-12-01
申请人： Junichi Tsuchimoto , Yutaka Inaba , Tamotsu Ogata , Kiyoshi Mori
发明人： Junichi Tsuchimoto , Yutaka Inaba , Tamotsu Ogata , Kiyoshi Mori
IPC分类号： H01L27/108 , H01L21/02 , H01L21/20 , H01L21/8242 , H10L21/8234
CPC分类号： H01L28/84 , H01L21/02532 , H01L21/02667 , H01L21/2022 , H01L27/10852
摘要： An amorphous silicon film is formed on an interlayer insulating film to cover an upper surface of the interlayer insulating film, and a side surface and a bottom surface of an opening formed at the interlayer insulating film. Phosphorus ions are implanted into the amorphous silicon film. The phosphorous ions are implanted into the amorphous silicon film located on the upper surface of the interlayer insulating film to prevent crystal grains from growing, and thus a polysilicon film having no hemispherical grains is formed. Accordingly, a semiconductor device having capacitors with respective storage nodes adjacent to each other that are electrically isolated properly is obtained.
摘要翻译：在层间绝缘膜上形成非晶硅膜以覆盖层间绝缘膜的上表面，以及形成在层间绝缘膜上的开口的侧表面和底表面。将磷离子注入到非晶硅膜中。将磷离子注入到位于层间绝缘膜的上表面的非晶硅膜中，以防止晶粒生长，从而形成不具有半球状晶粒的多晶硅膜。因此，获得具有彼此相邻的具有彼此电隔离的各个存储节点的电容器的半导体器件。

6. 发明申请

US20110291209A1 MAGNETIC MEMORY DEVICE 审中-公开
标题翻译：磁记忆装置
公开(公告)号：US20110291209A1
公开(公告)日：2011-12-01
申请号：US13150719
申请日：2011-06-01
申请人： Takashi TAKENAGA , Ryoji MATSUDA , Junichi TSUCHIMOTO
发明人： Takashi TAKENAGA , Ryoji MATSUDA , Junichi TSUCHIMOTO
IPC分类号： H01L29/82
CPC分类号： H01L27/228 , G11C11/161 , G11C11/1659 , G11C11/1675 , H01L43/08 , H01L43/10
摘要： To provide a magnetic memory device having an increased write current and improved reliability in writing. The magnetic memory device of the invention has a substrate, a write line provided over the substrate, a bit line placed with a space from the write line in a thickness direction of the substrate and extending in a direction crossing with an extending direction of the write line, and a magnetic memory element positioned between the write line and the bit line. The magnetic memory element has a pinned layer whose magnetization direction has been fixed and a recording layer whose magnetization direction changes, depending on an external magnetic field. The recording layer contains an alloy film. The alloy film contains cobalt, iron, and boron and its boron content exceeds 21 at %.
摘要翻译：提供具有增加的写入电流和提高写入可靠性的磁存储器件。本发明的磁存储装置具有基板，设置在基板上的写入线，沿着基板的厚度方向从写入线放置空间的位线，并且沿与写入的延伸方向交叉的方向延伸线和位于写入线和位线之间的磁存储元件。磁存储元件具有磁化方向固定的钉扎层和磁化方向根据外部磁场而变化的记录层。记录层含有合金膜。合金膜含有钴，铁和硼，其硼含量超过21原子％。

7. 发明申请

US20090263945A1 MANUFACTURING METHOD OF CMOS TYPE SEMICONDUCTOR DEVICE, AND CMOS TYPE SEMICONDUCTOR DEVICE 有权
标题翻译： CMOS型半导体器件的制造方法和CMOS型半导体器件
公开(公告)号：US20090263945A1
公开(公告)日：2009-10-22
申请号：US12492648
申请日：2009-06-26
申请人： Shimpei Tsujikawa , Yasuhiko Akamatsu , Hiroshi Umeda , Jiro Yugami , Masaharu Mizutani , Masao Inoue , Junichi Tsuchimoto , Kouji Nomura
发明人： Shimpei Tsujikawa , Yasuhiko Akamatsu , Hiroshi Umeda , Jiro Yugami , Masaharu Mizutani , Masao Inoue , Junichi Tsuchimoto , Kouji Nomura
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.
摘要翻译：在这种CMOS型半导体器件的制造方法中，能够抑制在栅极电极中含有硼的情况下，从pMOS晶体管的栅电极到半导体衬底的硼渗透，同时能够提高pMOS的NBTI寿命提供了晶体管，而不降低nMOS晶体管的性能。关于本发明的CMOS型半导体器件的制造方法具有以下工序。卤素引入pMOS晶体管形成区域的半导体衬底。接下来，在pMOS晶体管形成区域的半导体衬底上形成栅极绝缘膜。接下来，将氮引入到栅极绝缘膜。

8. 发明授权

US06756647B2 Semiconductor device including nitride layer 失效
公开(公告)号：US06756647B2
公开(公告)日：2004-06-29
申请号：US10370530
申请日：2003-02-24
申请人： Masao Inoue , Akinobu Teramoto , Junichi Tsuchimoto
发明人： Masao Inoue , Akinobu Teramoto , Junichi Tsuchimoto
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A semiconductor device includes an n-type semiconductor substrate including a source region and a drain region in a main surface thereof, a high-permittivity insulator film including a high permittivity material and formed to cover an upper side of a region of the main surface of n-type semiconductor substrate, which region is interposed between source region and drain region. And the semiconductor device includes a boron-doped gate electrode formed above high-permittivity insulator film, and a high-permittivity nitride layer formed between high-permittivity insulator film and boron-doped gate electrode.

9. 发明授权

US6069060A Method of manufacturing a semiconductor device having a single crystal silicon electrode 失效
标题翻译：制造具有单晶硅电极的半导体器件的方法
公开(公告)号：US6069060A
公开(公告)日：2000-05-30
申请号：US976597
申请日：1997-11-24
申请人： Masami Matsumoto , Junichi Tsuchimoto , Kiyoshi Mori
发明人： Masami Matsumoto , Junichi Tsuchimoto , Kiyoshi Mori
IPC分类号： H01L21/28 , H01L21/768 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108
CPC分类号： H01L27/10852
摘要： It is an object to obtain a semiconductor device free from a necessity of stacking a contact hole and a lower electrode, thus preventing occurrence of an error in stacking and enabling the capacitor to be formed precisely. Amorphous silicon 10b is deposited on a interlayer insulating film 9 including the inside portion of the contact hole 9a, and then a resist 14 is applied to the amorphous silicon 10b. Then, a mask for photolithography which has been used to form the contact hole 9a is used to perform a photolithography process to form the resist 14 to have a required shape. Then, implantation of phosphorus ions is performed such that the resist 14 is used as a mask 14a for preventing implantation of ions. Then, the amorphous silicon 10b is subjected to heat treatment to partially single crystallize the amorphous silicon 10b so that single crystal silicon 10c is grown. The difference in the etching rate between the amorphous silicon 10b and the single crystal silicon 10c is used to selectively remove the amorphous silicon 10b by using dry etching technique so that a storage node 10 is formed.
摘要翻译：本发明的目的是获得不需要堆叠接触孔和下电极的半导体器件，从而防止堆叠发生错误，并且能够精确地形成电容器。非晶硅10b沉积在包括接触孔9a的内部的层间绝缘膜9上，然后将抗蚀剂14施加到非晶硅10b。然后，使用已经用于形成接触孔9a的用于光刻的掩模来进行光刻工艺以形成具有所需形状的抗蚀剂14。然后，进行磷离子的注入，使得抗蚀剂14用作防止离子注入的掩模14a。然后，对非晶硅10b进行热处理，以使非晶硅10b部分单晶结晶，从而生长单晶硅10c。使用非晶硅10b和单晶硅10c之间的蚀刻速率的差异，通过使用干蚀刻技术来选择性地去除非晶硅10b，从而形成存储节点10。

10. 发明授权

US5426329A Semiconductor device with arsenic doped silicon thin film interconnections or electrodes 失效
标题翻译：具有砷掺杂硅薄膜互连或电极的半导体器件
公开(公告)号：US5426329A
公开(公告)日：1995-06-20
申请号：US296267
申请日：1994-08-25
申请人： Junichi Tsuchimoto
发明人： Junichi Tsuchimoto
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L23/532 , H01L29/45 , H01L23/48 , H01L23/40 , H01L29/62 , H01L29/64
CPC分类号： H01L23/53271 , H01L29/456 , H01L2924/0002
摘要： A principal feature of the present invention is to obtain a semiconductor device including a silicon thin film for use as interconnections or an electrode. The semiconductor device includes a semiconductor substrate, and a silicon thin film provided on the semiconductor substrate. Arsenic and carbon are added in the silicon thin film. The arsenic is distributed at a uniform concentration along a depth of the silicon thin film.
摘要翻译：本发明的主要特征是获得包括用作互连或电极的硅薄膜的半导体器件。半导体器件包括半导体衬底和设置在半导体衬底上的硅薄膜。在硅薄膜中加入砷和碳。砷以沿着硅薄膜的深度的均匀浓度分布。

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