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1. 发明申请

US20080176764A1 Oligomer probe array chips, masks used to produce the same, and hybridization analysis methods using the same 审中-公开
标题翻译：寡聚体探针阵列芯片，用于制备相同的掩模，以及使用其的杂交分析方法
公开(公告)号：US20080176764A1
公开(公告)日：2008-07-24
申请号：US12003131
申请日：2007-12-20
申请人： Jung-hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho
发明人： Jung-hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho
IPC分类号： C40B40/06 , B32B3/00 , G06K9/34
CPC分类号： B01J19/0046 , B01J2219/00387 , B01J2219/00527 , B01J2219/00576 , B01J2219/00596 , B01J2219/00608 , B01J2219/00659 , B01J2219/00662 , B01J2219/00693 , B01J2219/00702 , B01J2219/00722 , C12Q1/6837 , Y10T428/24612 , C12Q2565/513
摘要： Example embodiments may include an oligomer probe array chip based on an analysis-friendly layout. Example oligomer probe array chips may include a substrate, a main array on the substrate having a plurality of sub-arrays in rows or panels, and/or a plurality of alignment spot arrays outside of each of the sub-arrays. The sub-arrays may include a plurality of spots arranged in a matrix to which oligomer probes having different sequences may be attached. Example embodiments may further provide masks for fabricating oligomer probe array chips and hybridization analysis methods of oligomer probe array chips.
摘要翻译：示例性实施例可以包括基于分析友好布局的低聚物探针阵列芯片。示例性低聚物探针阵列芯片可以包括衬底，衬底上的主阵列具有排或面板中的多个子阵列，和/或每个子阵列外部的多个对准点阵列。子阵列可以包括布置在矩阵中的多个点，可以连接具有不同序列的低聚物探针。示例性实施例还可以提供用于制造低聚物探针阵列芯片的掩模和低聚物探针阵列芯片的杂交分析方法。

2. 发明授权

US08551759B2 Oligomer probe array and method of producing the same 失效
标题翻译：低聚物探针阵列及其制备方法
公开(公告)号：US08551759B2
公开(公告)日：2013-10-08
申请号：US11686506
申请日：2007-03-15
申请人： Jung-hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
发明人： Jung-hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
IPC分类号： C12M1/00 , C12M1/34 , C12Q1/68 , G01N33/53 , G01N33/551 , G01N33/552 , G01N33/545 , C07H21/02
CPC分类号： C12Q1/6834 , C12Q2563/155
摘要： An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.
摘要翻译：提供了具有改善的反应产率的低聚物探针阵列。低聚物探针阵列包括基底，基底上的固定层，与固定层的表面耦合的多个纳米颗粒以及与纳米颗粒表面结合的多个低聚物探针。

3. 发明申请

US20080038732A1 Oligomer Probe Array and Method of Producing the Same 失效
标题翻译：低聚物探针阵列及其制备方法
公开(公告)号：US20080038732A1
公开(公告)日：2008-02-14
申请号：US11686506
申请日：2007-03-15
申请人： Jung-Hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
发明人： Jung-Hwan Hah , Sung-min Chi , Kyoung-seon Kim , Won-sun Kim , Han-ku Cho , Sang-jun Choi , Man-hyoung Ryoo
IPC分类号： C12Q1/68 , C07H21/00
CPC分类号： C12Q1/6834 , C12Q2563/155
摘要： An oligomer probe array having improved reaction yield is provided. The oligomer probe array includes a substrate, an immobilization layer on the substrate, a plurality of nano particles coupled with a surface of the immobilization layer, and a plurality of oligomer probes coupled with surfaces of the nano particles.
摘要翻译：提供了具有改善的反应产率的低聚物探针阵列。低聚物探针阵列包括基底，基底上的固定层，与固定层的表面耦合的多个纳米颗粒以及与纳米颗粒的表面耦合的多个低聚物探针。

4. 发明申请

US20070023916A1 Semiconductor structure with multiple bottom anti-reflective coating layer and method of forming photoresist pattern and pattern of semiconductor device using the same structure 审中-公开
标题翻译：具有多个底部抗反射涂层的半导体结构和使用相同结构形成半导体器件的光致抗蚀剂图案和图案的方法
公开(公告)号：US20070023916A1
公开(公告)日：2007-02-01
申请号：US11494469
申请日：2006-07-28
申请人： Jung-hwan Hah , Yun-sook Chae , Han-ku Cho , Chang-jin Kang , Sang-gyun Woo , Man-hyoung Ryoo , Young-jae Jung
发明人： Jung-hwan Hah , Yun-sook Chae , Han-ku Cho , Chang-jin Kang , Sang-gyun Woo , Man-hyoung Ryoo , Young-jae Jung
IPC分类号： H01L23/52
CPC分类号： H01L21/31144 , G03F7/091 , H01L21/0276 , H01L21/32139
摘要： The semiconductor structure includes an etch target layer to be pattemed, a multiple bottom anti-reflective coating (BARC) layer, and a photoresist (PR) pattern. The multiple BARC layer includes a first mask layer formed on the etch target layer and containing carbon, and a second mask layer formed on the first mask layer and containing silicon. A PR layer formed on the multiple BARC layer undergoes photolithography to form the PR pattern on the multiple BARC layer. The multiple BARC layer has a reflectance of 2% or less, and an interface angle between the PR pattern and the multiple BARC layer is 80° to 90°.
摘要翻译：该半导体结构包括要被图案化的蚀刻目标层，多个底部抗反射涂层（BARC）层和光致抗蚀剂（PR）图案。多个BARC层包括形成在蚀刻靶层上并含有碳的第一掩模层和形成在第一掩模层上并含有硅的第二掩模层。形成在多个BARC层上的PR层经历光刻以在多个BARC层上形成PR图案。多个BARC层的反射率为2％以下，PR图案与多个BARC层之间的界面角为80°〜90°。

5. 发明申请

US20120021355A1 COATING COMPOSITION FOR DUV FILTERING, METHOD OF FORMING PHOTORESIST PATTERN USING THE SAME AND METHOD OF FABRICATING SEMICONDUCTOR DEVICE BY USING THE METHOD 有权
标题翻译：用于DUV过滤的涂料组合物，使用该方法形成光催化剂图案的方法和使用该方法制备半导体器件的方法
公开(公告)号：US20120021355A1
公开(公告)日：2012-01-26
申请号：US13188670
申请日：2011-07-22
申请人： Hyun-woo Kim , Hai-sub Na , Chil-hee Chung , Han-ku Cho
发明人： Hyun-woo Kim , Hai-sub Na , Chil-hee Chung , Han-ku Cho
IPC分类号： H01L21/311 , G03F7/039 , G03F7/26 , G02B5/22 , H01L21/02
CPC分类号： G03F7/0388 , G02B5/208 , G02B5/22 , G03F7/095 , G03F7/11
摘要： Provided are a coating composition for deep ultraviolet (DUV) filtering during an extreme ultraviolet (EUV) exposure, the coating composition including about 100 parts by weight of a solvent including a first solvent (the first solvent being an alcoholic solvent); and about 0.05 parts by weight to about 5 parts by weight of a coating polymer having a degree of absorption of about 50%/μm or greater with respect to 193-nm incident light.
摘要翻译：提供了一种在极紫外（EUV）暴露期间用于深紫外（DUV）过滤的涂料组合物，该涂料组合物包括约100重量份的包含第一溶剂（第一溶剂为醇溶剂）的溶剂; 和约0.05重量份至约5重量份的相对于193纳米入射光的吸收度为约50％/μm或更大的涂层聚合物。

6. 发明申请

US20110177437A1 Compensating Masks, Multi-Optical Systems Using the Masks, and Methods of Compensating for 3-D Mask Effect Using the Same 审中-公开
标题翻译：补偿面膜，使用面膜的多光学系统以及使用该面膜补偿三维掩模效果的方法
公开(公告)号：US20110177437A1
公开(公告)日：2011-07-21
申请号：US13079078
申请日：2011-04-04
申请人： Sung-soo Suh , Suk-joo Lee , Han-ku Cho , Yong-jin Chun , Sung-woo Lee , Young-chang Kim
发明人： Sung-soo Suh , Suk-joo Lee , Han-ku Cho , Yong-jin Chun , Sung-woo Lee , Young-chang Kim
IPC分类号： G03F1/00
CPC分类号： G03F1/36
摘要： Provided are a compensating mask, a multi-optical system using the compensating mask, and a method of compensating for a 3-dimensional (3-D) mask effect using the compensating mask. Methods of compensating for a 3-D mask effect using a compensating mask may include generating a first kernel corresponding to a normal mask used for forming a minute pattern, generating a second kernel corresponding to a compensating mask, mixing the first kernel corresponding to the normal mask with the second kernel corresponding to the compensating mask, and generating a multi-optical system kernel corresponding to mixing the first kernel and the second kernel.
摘要翻译：提供了补偿掩模，使用补偿掩模的多光学系统以及使用补偿掩模来补偿三维（3-D）掩模效应的方法。使用补偿掩模补偿3-D掩模效应的方法可以包括生成对应于用于形成微图案的正常掩模的第一内核，生成与补偿掩码相对应的第二内核，将与正常对应的第一内核混合掩模与第二核对应于补偿掩模，并且生成对应于混合第一内核和第二内核的多光学系统内核。

7. 发明授权

US07670761B2 Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key 失效
标题翻译：使用抗蚀剂回流测量键形成半导体器件的精细图案的方法
公开(公告)号：US07670761B2
公开(公告)日：2010-03-02
申请号：US12219214
申请日：2008-07-17
申请人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
发明人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
IPC分类号： G03F1/00
CPC分类号： H01L22/34 , G03F7/40 , H01L21/0273
摘要： In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.
摘要翻译：在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案，位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上首先回流钥匙

8. 发明申请

US20080076070A1 Methods of Forming Fine Patterns In Integrated Circuits Using Atomic Layer Deposition 审中-公开
标题翻译：在使用原子层沉积的集成电路中形成精细图案的方法
公开(公告)号：US20080076070A1
公开(公告)日：2008-03-27
申请号：US11554324
申请日：2006-10-30
申请人： Cha-won Koh , Han-ku Cho , Gi-sung Yeo , Yool Kang , Ji-young Lee , Doo-youl Lee
发明人： Cha-won Koh , Han-ku Cho , Gi-sung Yeo , Yool Kang , Ji-young Lee , Doo-youl Lee
IPC分类号： G03F7/00
CPC分类号： H01L21/31144 , H01L21/0273 , H01L21/0337 , H01L21/0338 , H01L21/32139 , H01L21/76816
摘要： A fine pattern is formed in an integrated circuit substrate, by forming a sacrificial pattern on the integrated circuit substrate. The sacrificial pattern includes tops and side walls. Atomic layer deposition is then performed to atomic layer deposit a mask material layer on the sacrificial pattern, including on the tops and the side walls thereof, and on the integrated circuit substrate therebetween. The mask material layer that was atomic layer deposited is then etched, to expose the top and the integrated circuit therebetween, such that a mask material pattern remains on the side walls. The sacrificial pattern is then removed, and the integrated circuit substrate is then etched through the mask material pattern that remains.
摘要翻译：通过在集成电路基板上形成牺牲图案，在集成电路基板上形成精细图案。牺牲图案包括顶部和侧壁。然后进行原子层沉积以在牺牲图案上沉积掩模材料层，包括在其顶部和侧壁上以及其间的集成电路基板上。然后蚀刻原子层沉积的掩模材料层，以暴露其间的顶部和集成电路，使得掩模材料图案残留在侧壁上。然后去除牺牲图案，然后通过保留的掩模材料图案蚀刻集成电路基板。

9. 发明授权

US07221014B2 DRAM devices having an increased density layout 失效
标题翻译：具有增加的密度布局的DRAM器件
公开(公告)号：US07221014B2
公开(公告)日：2007-05-22
申请号：US11015993
申请日：2004-12-17
申请人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
发明人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
IPC分类号： H01L29/74 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814
摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.
摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。提供了多个有源区域，其被电耦合到字线和位线。每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域可以由隔离区限定。

10. 发明申请

US20050064304A1 Mask for correcting optical proximity effect and method of manufacturing the same 失效
标题翻译：用于校正光学邻近效应的掩模及其制造方法
公开(公告)号：US20050064304A1
公开(公告)日：2005-03-24
申请号：US10982813
申请日：2004-11-08
申请人： Byeong-Soo Kim , Han-ku Cho
发明人： Byeong-Soo Kim , Han-ku Cho
IPC分类号： G03F1/00 , G03F1/29 , G03F1/32 , G03F1/34 , G03F1/36 , G03F1/68 , G03F1/70 , G03F1/80 , G03F7/20 , H01L21/027 , G03F9/00 , G03C5/00
CPC分类号： G03F1/34 , G03F1/29 , G03F1/36 , G03F7/70441
摘要： A mask corrects for an optical proximity effect (OPE). A dummy pattern having a phase-edge effect is formed on a mask substrate. The phase-edge effect reduces the intensity of light at the boundary of two transmitting regions from through transmitted light has a phase difference. A pattern can then be formed in a photolithographic process using the phase-edge effect. A difference between “isolated” and “dense” patterns formed on a wafer can be reduced by forming a dummy pattern in an isolated pattern region of the mask and making the diffraction pattern of the isolated pattern the same as that of the dense pattern, thereby improving the total focus margin. Because the intensity of light is reduced at the boundary between a first region in which the phase of the transmitted light is 0° and a second region in which the phase of the transmitted light is 180°, for example, a photoresist layer is not photosensitized.
摘要翻译：掩模校正光学邻近效应（OPE）。在掩模基板上形成具有相边效应的虚设图案。相位效应通过透射光降低两个透射区域的边界处的光强度，具有相位差。然后可以使用相缘效应在光刻工艺中形成图案。可以通过在掩模的隔离图案区域中形成虚设图案并使孤立图案的衍射图案与致密图案相同，从而可以减小在晶片上形成的“隔离”和“密集”图案之间的差异，由此提高总焦距。因为在透射光的相位为0°的第一区域和透射光的相位为180°的第二区域之间的边界处的光的强度例如光致抗蚀剂层不被光敏化。

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