专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20080280381A1 Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key 失效
标题翻译：使用抗蚀剂回流测量键形成半导体器件的精细图案的方法
公开(公告)号：US20080280381A1
公开(公告)日：2008-11-13
申请号：US12219214
申请日：2008-07-17
申请人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
发明人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
IPC分类号： H01L21/66
CPC分类号： H01L22/34 , G03F7/40 , H01L21/0273
摘要： In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.
摘要翻译：在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案，位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上首先回流钥匙

2. 发明申请

US20050089776A1 Resist reflow measurement key and method of forming a fine pattern of a semiconductor device using the same 审中-公开
标题翻译：阻抗回流测量键和使用其形成半导体器件的精细图案的方法
公开(公告)号：US20050089776A1
公开(公告)日：2005-04-28
申请号：US10937398
申请日：2004-09-10
申请人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
发明人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
IPC分类号： G03C5/00 , G03F7/40 , H01L21/027 , H01L21/3205 , H01L21/4763 , H01L23/544
CPC分类号： H01L22/34 , G03F7/40 , H01L21/0273
摘要： In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.
摘要翻译：在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案，位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上首先回流钥匙

3. 发明授权

US07670761B2 Method of forming a fine pattern of a semiconductor device using a resist reflow measurement key 失效
标题翻译：使用抗蚀剂回流测量键形成半导体器件的精细图案的方法
公开(公告)号：US07670761B2
公开(公告)日：2010-03-02
申请号：US12219214
申请日：2008-07-17
申请人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
发明人： Doo-youl Lee , Gi-sung Yeo , Han-ku Cho , Jung-hyeon Lee
IPC分类号： G03F1/00
CPC分类号： H01L22/34 , G03F7/40 , H01L21/0273
摘要： In a resist reflow measurement key, and method of fabricating a fine pattern of a semiconductor device using the same, the resist reflow measurement key includes a first reflow key including a plurality of first pattern elements each having a first pattern with a first radius of curvature located on a first side of a first center line and a second pattern with a second radius of curvature located on a second side of the first center line, and a second reflow key including a plurality of second pattern elements each having a third pattern with a third radius of curvature located on a first side of a second center line and a fourth pattern with a fourth radius of curvature located on a second side of the second center line, the second reflow key being formed on a same plane of a substrate as the first reflow key.
摘要翻译：在抗蚀剂回流测量键和使用其的半导体器件的精细图案的制造方法中，抗蚀剂回流测量键包括第一回流键，该第一回流键包括多个第一图案元素，每个第一图案元素具有第一曲率半径位于第一中心线的第一侧和位于第一中心线的第二侧上的具有第二曲率半径的第二图案，以及第二回流键，包括多个第二图案元素，每个第二图案元素具有第三图案，位于第二中心线的第一侧上的第三曲率半径和位于第二中心线的第二侧上的具有第四曲率半径的第四图案，第二回流键形成在与第二中心线相同的基板的同一平面上首先回流钥匙

4. 发明申请

US20050269615A1 Dram devices having an increased density layout 失效
标题翻译：具有增加密度布局的戏剧装置
公开(公告)号：US20050269615A1
公开(公告)日：2005-12-08
申请号：US11015993
申请日：2004-12-17
申请人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
发明人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/02 , H01L29/74
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814
摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.
摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。提供了多个有源区域，其被电耦合到字线和位线。每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域可以由隔离区限定。

5. 发明授权

US07221014B2 DRAM devices having an increased density layout 失效
标题翻译：具有增加的密度布局的DRAM器件
公开(公告)号：US07221014B2
公开(公告)日：2007-05-22
申请号：US11015993
申请日：2004-12-17
申请人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
发明人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
IPC分类号： H01L29/74 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814
摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.
摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。提供了多个有源区域，其被电耦合到字线和位线。每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域可以由隔离区限定。

6. 发明申请

US20080124931A1 Method for forming fine patterns of a semiconductor device using a double patterning process 失效
标题翻译：使用双重图案形成工艺形成半导体器件的精细图案的方法
公开(公告)号：US20080124931A1
公开(公告)日：2008-05-29
申请号：US11978718
申请日：2007-10-30
申请人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
发明人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76838
摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案，在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为蚀刻掩模以形成蚀刻膜图案。

7. 发明授权

US07892982B2 Method for forming fine patterns of a semiconductor device using a double patterning process 失效
标题翻译：使用双重图案形成工艺形成半导体器件的精细图案的方法
公开(公告)号：US07892982B2
公开(公告)日：2011-02-22
申请号：US11978718
申请日：2007-10-30
申请人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
发明人： Doo-youl Lee , Pan-suk Kwak , Sung-gon Jung , Jung-hyeon Lee , Suk-joo Lee , Cha-won Koh , Ji-young Lee
IPC分类号： H01L21/302
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/0338 , H01L21/31144 , H01L21/76816 , H01L21/76838
摘要： A method for forming fine patterns of a semiconductor device includes forming an etching film on a substrate having first and second areas, forming first mask patterns on the substrate to have a first pattern density in the first area and a second pattern density in the second area, forming first capping patterns between the first mask patterns, forming second capping patterns between the first mask patterns, such that recess areas are formed between second capping patterns, and such that a first etching pattern is defined to include the first and second capping patterns, forming second mask patterns in the recess areas to include the first and second mask patterns, removing one of the first and second etching patterns, such that a single etching pattern is remaining on the substrate, and etching the etching film using the remaining etching pattern as an etch mask to form etching film patterns.
摘要翻译：用于形成半导体器件的精细图案的方法包括在具有第一和第二区域的衬底上形成蚀刻膜，在衬底上形成第一掩模图案以在第一区域中具有第一图案密度，在第二区域中形成第二图案密度在所述第一掩模图案之间形成第一封盖图案，在所述第一掩模图案之间形成第二封盖图案，使得在第二封盖图案之间形成凹陷区域，并且使得第一蚀刻图案被限定为包括所述第一和第二封盖图案，在凹陷区域中形成第二掩模图案以包括第一和第二掩模图案，去除第一和第二蚀刻图案中的一个，使得在基板上残留单个蚀刻图案，并使用剩余的蚀刻图案蚀刻蚀刻膜作为蚀刻掩模以形成蚀刻膜图案。

8. 发明授权

US07205241B2 Method for manufacturing semiconductor device with contact body extended in direction of bit line 失效
标题翻译：具有沿位线方向延伸的接触体的半导体器件的制造方法
公开(公告)号：US07205241B2
公开(公告)日：2007-04-17
申请号：US10731931
申请日：2003-12-10
申请人： Chang-min Park , Jung-hyeon Lee , Han-ku Cho , Joon-soo Park
发明人： Chang-min Park , Jung-hyeon Lee , Han-ku Cho , Joon-soo Park
IPC分类号： H01L21/302
CPC分类号： H01L21/76897 , H01L21/76895 , H01L27/10855 , H01L27/10894 , H01L28/91 , Y10S438/942
摘要： Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.
摘要翻译：提供了制造具有沿位线方向延伸的接触体以增加接触体与存储电极之间的接触面积的半导体器件的方法。在一个方面，一种方法包括在半导体衬底上形成栅极线，形成第一绝缘层以覆盖栅极线，形成第一接触焊盘和第二接触焊盘，这些接触焊盘和第二接触焊盘通过穿透栅极线与半导体衬底电连接第一绝缘层。此外，形成第二绝缘层以覆盖第一接触焊盘和第二接触焊盘，并且位线横跨栅极线形成，并且通过穿透第二绝缘层而电连接到第二接触焊盘。此外，形成第三绝缘层以覆盖位线，并且被选择性地蚀刻以形成穿过位线并暴露第一接触焊盘的带状开口。

9. 发明授权

US06492701B1 Semiconductor device having anti-reflective cap and spacer, method of manufacturing the same, and method of manufacturing photoresist pattern using the same 失效
标题翻译：具有抗反射盖和间隔物的半导体器件及其制造方法以及使用其制造光刻胶图案的方法
公开(公告)号：US06492701B1
公开(公告)日：2002-12-10
申请号：US09324072
申请日：1999-06-01
申请人： In-sung Kim , Jung-hyeon Lee , Han-ku Cho
发明人： In-sung Kim , Jung-hyeon Lee , Han-ku Cho
IPC分类号： H01L310232
CPC分类号： H01L21/0276 , H01L21/28044 , H01L21/28061 , H01L21/76802
摘要： A semiconductor device including an anti-reflective cap and spacer, a method of manufacturing the same, and a method of forming a photoresist pattern using the same are provided. The semiconductor device according to the present invention includes an anti-reflective cap and an anti-reflective spacer on an upper surface and side walls of a reflective pattern formed on the semiconductor substrate. Therefore, the deformation of the photoresist pattern by the light reflected from the reflective pattern is minimized during a photolithography process.
摘要翻译：提供了包括抗反射盖和间隔物的半导体器件，其制造方法和使用其形成光致抗蚀剂图案的方法。根据本发明的半导体器件包括在半导体衬底上形成的反射图案的上表面上的抗反射盖和抗反射隔板。因此，在光刻工艺中，由反射图案反射的光使光刻胶图案的变形最小化。

10. 发明授权

US06381165B1 Semiconductor memory device having storage node electrodes offset from each other 有权
标题翻译：具有彼此偏移的存储节点电极的半导体存储器件
公开(公告)号：US06381165B1
公开(公告)日：2002-04-30
申请号：US09966785
申请日：2001-09-28
申请人： Jung-hyeon Lee , Han-ku Cho
发明人： Jung-hyeon Lee , Han-ku Cho
IPC分类号： G11C502
CPC分类号： H01L27/10808 , G11C5/025 , H01L27/0207
摘要： A semiconductor memory device that is capable of reducing the probability of a bridge being generated between storage node electrodes, and a mask pattern for defining the storage node electrodes, are provided. The semiconductor memory device includes a plurality of storage node electrodes that are vertically and horizontally arranged a predetermined distance apart in columns and rows, respectively. Among the plurality of storage node electrodes, storage node electrodes belonging to even-numbered columns are shifted up or down a predetermined distance. The shifted storage node electrodes are shifted in a gap between vertically adjacent storage node electrodes belonging to a same column.
摘要翻译：提供了能够降低在存储节点电极之间产生桥的可能性的半导体存储器件，以及用于限定存储节点电极的掩模图案。半导体存储器件包括分别沿列和行分别垂直和水平布置成预定距离的多个存储节点电极。在多个存储节点电极中，属于偶数列的存储节点电极向上或向下移动预定距离。偏移的存储节点电极在属于同一列的垂直相邻的存储节点电极之间的间隙中偏移。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式