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1. 发明授权

US07221014B2 DRAM devices having an increased density layout 失效
标题翻译：具有增加的密度布局的DRAM器件
公开(公告)号：US07221014B2
公开(公告)日：2007-05-22
申请号：US11015993
申请日：2004-12-17
申请人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
发明人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
IPC分类号： H01L29/74 , H01L29/76
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814
摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.
摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。提供了多个有源区域，其被电耦合到字线和位线。每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域可以由隔离区限定。

2. 发明申请

US20050269615A1 Dram devices having an increased density layout 失效
标题翻译：具有增加密度布局的戏剧装置
公开(公告)号：US20050269615A1
公开(公告)日：2005-12-08
申请号：US11015993
申请日：2004-12-17
申请人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
发明人： Doo-hoon Goo , Jung-hyeon Lee , Gi-sung Yeo , Han-ku Cho , Sang-gyun Woo
IPC分类号： H01L27/108 , H01L21/8242 , H01L27/02 , H01L29/74
CPC分类号： H01L27/10888 , H01L27/0207 , H01L27/10814
摘要： DRAM devices include a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction and intersecting the word lines. A plurality of active regions is provided that are electrically coupled to the word lines and the bit lines. Each of the active regions defines a single unit memory cell having an area of 6F2 in terms of a minimum line width F. Each of the active regions may be overlapped by only one word line and the active regions may be defined by an isolation region.
摘要翻译： DRAM装置包括沿第一方向延伸的多个字线和沿第二方向延伸并与字线相交的多个位线。提供了多个有源区域，其被电耦合到字线和位线。每个有源区域以最小线宽度F来限定具有6F 2的面积的单个单元存储单元。每个有源区域可以仅由一条字线重叠，并且有源区域可以由隔离区限定。

3. 发明申请

US20050266646A1 Method of forming trench in semiconductor device 失效
标题翻译：在半导体器件中形成沟槽的方法
公开(公告)号：US20050266646A1
公开(公告)日：2005-12-01
申请号：US11080891
申请日：2005-03-16
申请人： Doo-hoon Goo , Si-hyeung Lee , Han-ku Cho , Sang-gyun Woo , Gi-sung Yeo
发明人： Doo-hoon Goo , Si-hyeung Lee , Han-ku Cho , Sang-gyun Woo , Gi-sung Yeo
IPC分类号： H01L21/76 , H01L21/00 , H01L21/308 , H01L21/8242 , H01L27/02
CPC分类号： H01L27/10876 , H01L21/3083 , H01L27/0207
摘要： There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.
摘要翻译：提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局包括不连续对准的多个开放区域的对准。使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

4. 发明授权

US07259065B2 Method of forming trench in semiconductor device 失效
标题翻译：在半导体器件中形成沟槽的方法
公开(公告)号：US07259065B2
公开(公告)日：2007-08-21
申请号：US11080891
申请日：2005-03-16
申请人： Doo-hoon Goo , Si-hyeung Lee , Han-ku Cho , Sang-gyun Woo , Gi-sung Yeo
发明人： Doo-hoon Goo , Si-hyeung Lee , Han-ku Cho , Sang-gyun Woo , Gi-sung Yeo
IPC分类号： H01L21/336
CPC分类号： H01L27/10876 , H01L21/3083 , H01L27/0207
摘要： There are provided a method of forming a trench for a recessed channel of a transistor and a layout for the same. A layout for the recessed channel according to one aspect of the present invention is formed such that an open region is extended across at least one of a first active region in a lateral direction, and also across another second active region in parallel with the first active region in a diagonal direction, and the extension is cut not to reach an isolation region between two third active regions that are in parallel with the second active region in a diagonal direction, and have noses facing each other in a longitudinal direction, and the layout includes an alignment of a plurality of open regions, which are discontinuously aligned. An etch mask is formed using the layout, and a semiconductor substrate is etched using the etch mask, and a trench for a recessed channel is formed on the active region.
摘要翻译：提供了一种形成用于晶体管的凹槽的沟槽的方法及其布局。根据本发明的一个方面的凹陷通道的布局被形成为使得开放区域跨越横向方向上的第一有源区域中的至少一个延伸，并且还跨越与第一活性物体平行的另一个第二有源区域区域，并且延伸部被切割成不能在对角线方向上到达与第二有源区域平行的两个第三有源区域之间的隔离区域，并且在纵向方向上具有彼此面对的鼻子，并且布局包括不连续对准的多个开放区域的对准。使用布局形成蚀刻掩模，并且使用蚀刻掩模蚀刻半导体衬底，并且在有源区上形成用于凹陷沟道的沟槽。

5. 发明申请

US20070284623A1 Semiconductor device having vertical channel transistor 审中-公开
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US20070284623A1
公开(公告)日：2007-12-13
申请号：US11802647
申请日：2007-05-24
申请人： Sang-Jin Kim , Gi-sung Yeo , Joon-soo Park , Han-ku Cho , Sang-gyun Woo , Min-jong Hong
发明人： Sang-Jin Kim , Gi-sung Yeo , Joon-soo Park , Han-ku Cho , Sang-gyun Woo , Min-jong Hong
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L27/0207 , H01L27/10823 , H01L27/10876 , H01L29/4236 , H01L29/66666 , H01L29/7827
摘要： A semiconductor device includes a substrate, and a plurality of active pillars arranged in a pattern of alternating even and odd rows and alternating even and odd columns, each active pillar extending from the substrate and including a channel portion, wherein the odd columns include active pillars spaced at a first pitch, the first pitch being determined in the column direction, the even columns include active pillars spaced at the first pitch, the even rows include active pillars spaced at a third pitch, the third pitch being determined in the row direction the odd rows include active pillars spaced at the third pitch, and active pillars in the even columns are offset by a second pitch from active pillars in the odd columns, the second pitch being determined in the column direction.
摘要翻译：半导体器件包括衬底和布置成交替的偶数行和奇数行以及交替的偶数和奇数列的多个有源柱，每个有源柱从衬底延伸并且包括沟道部分，其中奇数列包括有源柱以第一间距间隔开，第一间距是在列方向上确定的，偶数列包括以第一节距间隔开的活动柱，偶数行包括以第三节距间隔开的有效柱，第三间距在行方向上确定奇数行包括在第三间距处间隔开的活动柱，并且偶数列中的活动柱由奇数列中的活动柱偏移第二间距，第二间距在列方向上确定。

6. 发明申请

US20070023916A1 Semiconductor structure with multiple bottom anti-reflective coating layer and method of forming photoresist pattern and pattern of semiconductor device using the same structure 审中-公开
标题翻译：具有多个底部抗反射涂层的半导体结构和使用相同结构形成半导体器件的光致抗蚀剂图案和图案的方法
公开(公告)号：US20070023916A1
公开(公告)日：2007-02-01
申请号：US11494469
申请日：2006-07-28
申请人： Jung-hwan Hah , Yun-sook Chae , Han-ku Cho , Chang-jin Kang , Sang-gyun Woo , Man-hyoung Ryoo , Young-jae Jung
发明人： Jung-hwan Hah , Yun-sook Chae , Han-ku Cho , Chang-jin Kang , Sang-gyun Woo , Man-hyoung Ryoo , Young-jae Jung
IPC分类号： H01L23/52
CPC分类号： H01L21/31144 , G03F7/091 , H01L21/0276 , H01L21/32139
摘要： The semiconductor structure includes an etch target layer to be pattemed, a multiple bottom anti-reflective coating (BARC) layer, and a photoresist (PR) pattern. The multiple BARC layer includes a first mask layer formed on the etch target layer and containing carbon, and a second mask layer formed on the first mask layer and containing silicon. A PR layer formed on the multiple BARC layer undergoes photolithography to form the PR pattern on the multiple BARC layer. The multiple BARC layer has a reflectance of 2% or less, and an interface angle between the PR pattern and the multiple BARC layer is 80° to 90°.
摘要翻译：该半导体结构包括要被图案化的蚀刻目标层，多个底部抗反射涂层（BARC）层和光致抗蚀剂（PR）图案。多个BARC层包括形成在蚀刻靶层上并含有碳的第一掩模层和形成在第一掩模层上并含有硅的第二掩模层。形成在多个BARC层上的PR层经历光刻以在多个BARC层上形成PR图案。多个BARC层的反射率为2％以下，PR图案与多个BARC层之间的界面角为80°〜90°。

7. 发明申请

US20060115746A1 Focus monitoring masks having multiple phase shifter units and methods for fabricating the same 审中-公开
标题翻译：具有多个移相器单元的聚焦监视掩模及其制造方法
公开(公告)号：US20060115746A1
公开(公告)日：2006-06-01
申请号：US11280606
申请日：2005-11-16
申请人： Sung-Won Choi , Suk-joo Lee , Ho-chul Kim , Han-ku Cho , Sang-gyun Woo
发明人： Sung-Won Choi , Suk-joo Lee , Ho-chul Kim , Han-ku Cho , Sang-gyun Woo
IPC分类号： G03C5/00 , G03F1/00
CPC分类号： G03F1/28 , G03F1/44 , G03F7/70641
摘要： A focus monitoring mask includes a transparent substrate, e.g., a quartz layer. A light blocking film, e.g., a chromium-containing film, is disposed on the transparent substrate and has an opening therein. A transparent unit is disposed in a portion of the substrate exposed by the opening. The transparent unit includes a first phase shifter, a second phase shifter and a third phase shifter arranged adjacently in order of amount of phase shift. The second phase shifter is configured to provide an about 180° phase difference with respect to the first phase shifter. The third phase shifter is configured to provide a phase difference other than about 0° and about 180° with respect to the first phase shifter. The transparent unit may further include a fourth phase shifter having a fourth phase difference with respect to the first phase shifter that differs from about 0°, about 180° and the phase difference provided by the third phase shifter.
摘要翻译：焦点监视掩模包括透明衬底，例如石英层。遮光膜例如含铬膜设置在透明基板上并具有开口。透明单元设置在由开口暴露的基板的一部分中。透明单元包括第一移相器，第二移相器和第三移相器，其以相移量的顺序相邻布置。第二移相器被配置为相对于第一移相器提供约180°的相位差。第三移相器被配置为相对于第一移相器提供除了约0°和约180°之外的相位差。透明单元还可以包括相对于第一移相器具有第四相位差的第四移相器，其不同于约0°，约180°以及由第三移相器提供的相位差。

8. 发明授权

US08242018B2 Semiconductor device having fine contacts and method of fabricating the same 有权
标题翻译：具有微细接触的半导体器件及其制造方法
公开(公告)号：US08242018B2
公开(公告)日：2012-08-14
申请号：US12943142
申请日：2010-11-10
申请人： Ji-young Lee , Hyun-jae Kang , Sang-gyun Woo
发明人： Ji-young Lee , Hyun-jae Kang , Sang-gyun Woo
IPC分类号： H01L21/44
CPC分类号： H01L21/76816 , H01L21/76897
摘要： A semiconductor device has a structure of contacts whose size and pitch are finer that those that can be produced under the resolution provided by conventional photolithography. The contact structure includes a semiconductor substrate, an interlayer insulating layer disposed on the substrate, annular spacers situated in the interlayer insulating layer, first contacts surrounded by the spacers, and a second contact buried in the interlayer insulating layer between each adjacent pair of the first spacers. The contact structure is formed by forming first contact holes in the interlayer insulating layer, forming the spacers over the sides of the first contact holes to leave second contact holes within the first contact holes, etching the interlayer insulating layer from between the spacers using the first spacers as an etch mask to form third contact holes, and filling the first and second contact holes with conductive material. In this way, the pitch of the contacts can be half that of the first contact holes.
摘要翻译：半导体器件具有接触的结构，其尺寸和间距比通过常规光刻提供的分辨率可以产生的那些更小。所述接触结构包括半导体衬底，设置在所述衬底上的层间绝缘层，位于所述层间绝缘层中的环形间隔物，被所述间隔物包围的第一接触部以及埋在所述层间绝缘层中的每个相邻的所述第一接触层间隔物接触结构通过在层间绝缘层中形成第一接触孔而形成，在第一接触孔的侧面上形成间隔物以在第一接触孔内留下第二接触孔，使用第一接触孔从间隔物之间蚀刻层间绝缘层间隔物作为蚀刻掩模以形成第三接触孔，并且用导电材料填充第一和第二接触孔。以这种方式，触点的间距可以是第一接触孔的间距的一半。

9. 发明授权

US07361609B2 Mask patterns for semiconductor device fabrication and related methods 失效
标题翻译：半导体器件制造的掩模图案及相关方法
公开(公告)号：US07361609B2
公开(公告)日：2008-04-22
申请号：US11232703
申请日：2005-09-22
申请人： Jung-hwan Hah , Hyun-woo Kim , Mitsuhiro Hata , Sang-gyun Woo
发明人： Jung-hwan Hah , Hyun-woo Kim , Mitsuhiro Hata , Sang-gyun Woo
IPC分类号： H01L21/302
CPC分类号： H01L21/0274 , G03F7/405 , H01L21/0273 , H01L21/31144
摘要： Methods of forming an integrated circuit device may include forming a resist pattern on a layer of an integrated circuit device with portions of the layer being exposed through openings of the resist pattern. An organic-inorganic hybrid siloxane network film may be formed on the resist pattern. Portions of the layer exposed through the resist pattern and the organic-inorganic hybrid siloxane network film may then be removed. Related structures are also discussed.
摘要翻译：形成集成电路器件的方法可以包括在集成电路器件的层上形成抗蚀剂图案，其中该层的部分通过抗蚀剂图案的开口露出。可以在抗蚀剂图案上形成有机 - 无机杂化硅氧烷网膜。然后可以去除通过抗蚀剂图案暴露的层的部分和有机 - 无机杂化硅氧烷网膜。还讨论了相关结构。

10. 发明授权

US06596459B1 Photosensitive polymer and resist composition containing the same 失效
标题翻译：含有它们的光敏聚合物和抗蚀剂组合物
公开(公告)号：US06596459B1
公开(公告)日：2003-07-22
申请号：US09716269
申请日：2000-11-21
申请人： Hyun-woo Kim , Ki-young Kwon , Si-hyeung Lee , Dong-won Jung , Sook Lee , Kwang-sub Yoon , Sang-jun Choi , Sang-gyun Woo
发明人： Hyun-woo Kim , Ki-young Kwon , Si-hyeung Lee , Dong-won Jung , Sook Lee , Kwang-sub Yoon , Sang-jun Choi , Sang-gyun Woo
IPC分类号： G03F7004
CPC分类号： G03F7/0395 , G03F7/0397
摘要： There are provided a photosensitive polymer and a photoresist compositing containing the same. The photosensitive polymer is represented by the following formula: wherein R1 is an acid-labile tertiary alkyl ester group, R2 is hydrogen atom, methyl, ethyl, carboxyl, &ggr;-butyrolactone-2-yl ester, &ggr;-butyrolactone-3-yl ester, pantolactone-2-yl ester, mevalonic lactone ester, 3-tetrahydrofuranyl ester, 2,3-propylenecarbonate-1-yl ester, 3-methyl-&ggr;-butyrolactone-3-yl ester or C3 to C20 alicyclic hydrocarbon, a/(a+b+c) is 0.1˜0.7, b/(a+b+c) is 0.1˜0.8, c/(a+b+c) is 0.0˜0.8, and n is an integer in the range of 0 to 2.
摘要翻译：提供光敏聚合物和含有它的光致抗蚀剂复合物。光敏聚合物由下式表示：其中R1是酸不稳定的叔烷基酯基，R2是氢原子，甲基，乙基，羧基，γ-丁内酯-2-基酯，γ-丁内酯-3-基酯，泛酸内酯-2-基酯，甲羟戊酸内酯，3-四氢呋喃基酯，2,3-亚丙基碳酸酯-1-基酯，3-甲基-γ-丁内酯-3-基酯或C 3至C 20脂环族烃，a /（ a + b + c）为0.1〜0.7，b /（a + b + c）为0.1〜0.8，c /（a + b + c）为0.0〜0.8，n为0〜 2。

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