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1. 发明授权

US06737335B2 Shallow trench isolation type semiconductor device and method of manufacturing the same 失效
标题翻译：浅沟槽隔离型半导体器件及其制造方法
公开(公告)号：US06737335B2
公开(公告)日：2004-05-18
申请号：US10440806
申请日：2003-05-19
申请人： Jung-Dal Choi , Kyu-Charn Park , Dong-Seog Eun
发明人： Jung-Dal Choi , Kyu-Charn Park , Dong-Seog Eun
IPC分类号： H01L2176
CPC分类号： H01L27/11526 , H01L21/76229 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11541 , Y10S438/981
摘要： A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.
摘要翻译：浅沟槽隔离型半导体器件包括在第一区域和第二区域中形成的栅极绝缘层。栅极绝缘层相对于第二区域中的栅极绝缘层的厚度在第一区域中具有更大的厚度。在第一区域和第二区域中还形成浅沟槽隔离层，第一区域中的浅沟槽隔离层比第二区域中的浅沟槽隔离层更薄。

2. 发明授权

US06586804B2 Shallow trench isolation type semiconductor device and method of manufacturing the same 失效
公开(公告)号：US06586804B2
公开(公告)日：2003-07-01
申请号：US09949110
申请日：2001-09-07
申请人： Jung-Dal Choi , Kyu-Charn Park , Dong-Seog Eun
发明人： Jung-Dal Choi , Kyu-Charn Park , Dong-Seog Eun
IPC分类号： H01L2978
CPC分类号： H01L27/11526 , H01L21/76229 , H01L21/823462 , H01L21/823481 , H01L27/105 , H01L27/11541 , Y10S438/981
摘要： A shallow trench isolation type semiconductor device includes a gate insulating layer formed in a first region and in a second region. The gate insulating layer is of greater thickness in the first region, relative to the thickness of the gate insulating layer in the second region. A shallow trench isolation layer is also formed in the first region and the second region, the shallow trench isolation layer in the first region being thinner than shallow trench isolation layer in the second region.

3. 发明授权

US06979628B2 Methods of forming semiconductor devices having field oxides in trenches and devices formed thereby 有权
标题翻译：在沟槽中形成具有场氧化物的半导体器件和由此形成的器件的方法
公开(公告)号：US06979628B2
公开(公告)日：2005-12-27
申请号：US10726788
申请日：2003-12-02
申请人： Hong-Soo Kim , Kyu-Charn Park , Jung-Dal Choi , Seong-Soon Cho
发明人： Hong-Soo Kim , Kyu-Charn Park , Jung-Dal Choi , Seong-Soon Cho
IPC分类号： H01L21/76 , H01L21/762
CPC分类号： H01L21/76229 , H01L21/76205 , H01L21/76213 , H01L21/76232 , H01L21/76237
摘要： Semiconductor devices and methods of forming devices that have field oxides in trenches are disclosed. According to the methods, a semiconductor substrate is prepared. An upper trench is formed at a predetermined region of the semiconductor substrate and a bottom trench is formed at a bottom surface of the upper trench. A field oxide is formed to fill the bottom trench and the upper trench. At this time, the upper trench has a wider width than the bottom trench.
摘要翻译：公开了在沟槽中形成具有场氧化物的器件的半导体器件和方法。根据该方法制备半导体衬底。在半导体衬底的预定区域处形成上沟槽，并且在上沟槽的底表面处形成底沟槽。形成场氧化物以填充底部沟槽和上部沟槽。此时，上沟槽的宽度比底沟宽。

4. 发明授权

US06936885B2 NAND-type flash memory devices and methods of fabricating the same 有权
公开(公告)号：US06936885B2
公开(公告)日：2005-08-30
申请号：US10921656
申请日：2004-08-19
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115 , H01L27/11524
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.

5. 发明授权

US07508048B2 Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法
公开(公告)号：US07508048B2
公开(公告)日：2009-03-24
申请号：US10758802
申请日：2004-01-15
申请人： Dae-Woong Kang , Hong-Soo Kim , Jung-Dal Choi , Kyu-Charn Park , Seong-Soon Cho , Yong-Sik Yim , Sung-Nam Chang
发明人： Dae-Woong Kang , Hong-Soo Kim , Jung-Dal Choi , Kyu-Charn Park , Seong-Soon Cho , Yong-Sik Yim , Sung-Nam Chang
IPC分类号： H01L29/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11526 , H01L27/11543
摘要： Methods of fabricating a semiconductor device having multi-gate insulation layers and semiconductor devices fabricated thereby are provided. The method includes forming a pad insulation layer and an initial high voltage gate insulation layer on a first region and a second region of a semiconductor substrate respectively. The initial high voltage gate insulation layer is formed to be thicker than the pad insulation layer. A first isolation layer that penetrates the pad insulation layer and is buried in the semiconductor substrate is formed to define a first active region in the first region, and a second isolation layer that penetrates the initial high voltage gate insulation layer and is buried in the semiconductor substrate is formed to define a second active region in the second region. The pad insulation layer is then removed to expose the first active region. A low voltage gate insulation layer is formed on the exposed first active region. Accordingly, it can minimize a depth of recessed regions (dent regions) to be formed at edge regions of the first isolation layer during removal of the pad insulation layer, and it can prevent dent regions from being formed at edge regions of the second isolation layer.
摘要翻译：提供了制造具有多栅极绝缘层的半导体器件和由此制造的半导体器件的方法。该方法包括分别在半导体衬底的第一区域和第二区域上形成衬垫绝缘层和初始高电压栅极绝缘层。初始高压栅绝缘层形成为比焊垫绝缘层厚。形成穿过焊盘绝缘层并被埋在半导体衬底中的第一隔离层，以限定第一区域中的第一有源区和穿过初始高电压栅极绝缘层并被埋在半导体中的第二隔离层形成衬底以限定第二区域中的第二有源区。然后去除焊盘绝缘层以露出第一有源区。在暴露的第一有源区上形成低压栅极绝缘层。因此，能够最大限度地减少在去除焊盘绝缘层期间在第一隔离层的边缘区域形成的凹陷区域（凹陷区域）的深度，并且可以防止凹陷区域形成在第二隔离层的边缘区域。

6. 发明授权

US06960500B2 Semiconductor device and method of manufacturing the same including forming metal silicide gate lines and source lines 有权
标题翻译：半导体器件及其制造方法，包括形成金属硅化物栅极线和源极线
公开(公告)号：US06960500B2
公开(公告)日：2005-11-01
申请号：US10777233
申请日：2004-02-11
申请人： You-Cheol Shin , Kyu-Charn Park , Won-Hong Lee , Jung-Dal Choi
发明人： You-Cheol Shin , Kyu-Charn Park , Won-Hong Lee , Jung-Dal Choi
IPC分类号： H01L21/28 , H01L21/00 , H01L21/336 , H01L21/4763 , H01L21/82 , H01L21/8238 , H01L21/8247 , H01L27/108 , H01L27/115 , H01L29/04 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
摘要翻译：一种半导体器件包括多个栅极线，其由在多个晶体管中用作栅电极的线形构成，并且通过栅极绝缘层与基板分离，各自具有上金属硅化物层; 以及仅通过进行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。

7. 发明授权

US06720579B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06720579B2
公开(公告)日：2004-04-13
申请号：US10041732
申请日：2002-01-07
申请人： You-Cheol Shin , Kyu-Charn Park , Won-Hong Lee , Jung-Dal Choi
发明人： You-Cheol Shin , Kyu-Charn Park , Won-Hong Lee , Jung-Dal Choi
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , H01L27/115
摘要： A semiconductor device comprises a plurality of gate lines composed of line shapes to function as gate electrodes in a plurality of transistors and separated from a substrate by a gate insulating layer, each having an upper metal silicide layer; and a plurality of source/drain regions formed on the substrate between said gate lines solely by carrying out impurity implantation processes.
摘要翻译：一种半导体器件包括多个栅极线，其由在多个晶体管中用作栅电极的线形构成，并且通过栅极绝缘层与基板分离，各自具有上金属硅化物层; 以及仅通过进行杂质注入工艺而在所述栅极线之间的衬底上形成的多个源极/漏极区域。

8. 发明授权

US06624464B2 Highly integrated non-volatile memory cell array having a high program speed 有权
公开(公告)号：US06624464B2
公开(公告)日：2003-09-23
申请号：US10001460
申请日：2001-10-29
申请人： Kwang-Shik Shin , Kyu-Charn Park , Sung-Nam Chang , Jung-Dal Choi , Won-Hong Lee
发明人： Kwang-Shik Shin , Kyu-Charn Park , Sung-Nam Chang , Jung-Dal Choi , Won-Hong Lee
IPC分类号： H01L2976
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： A non-volatile memory cell array having second floating gates with a narrow width, a large height, and slanted side walls. Critical dimension errors due to photolithographic and etching processes are decreased. The difference in the coupling ratio between the memory cells is low thereby improving speed during programming and/or erasing. A second floating gate having a narrower critical dimension than a second floating gate obtained using a photolithographic process may be designed, thereby forming a highly integrated non-volatile memory cell array.

9. 发明授权

US06521941B2 Non-volatile memory device and fabrication method thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US06521941B2
公开(公告)日：2003-02-18
申请号：US09861213
申请日：2001-05-17
申请人： Kyu-Charn Park , Jung-Dal Choi , Yong-Sik Yim
发明人： Kyu-Charn Park , Jung-Dal Choi , Yong-Sik Yim
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11529 , H01L27/11531 , H01L29/42324 , H01L29/511
摘要： A non-volatile memory device and fabrication methods thereof are provided. A first inter-gate insulating layer is formed to intervene between control gate electrodes and floating gate electrodes in a cell array area. A second inter-gate insulating layer is formed to intervene between a gate electrode and a dummy gate electrode in a peripheral circuit area. The second inter-gate insulating layer has a thickness greater than a thickness of the first inter-gate insulating layer on a top surface of the floating gate electrodes. By reducing the difference between the thickness of the first inter-gate insulating layer on sidewalls of floating gate patterns and the thickness of the second inter-gate insulating layer on a gate electrode pattern, in accordance with the invention, any etching damage to the substrate in the peripheral circuit area can be considerably reduced or prevented during the fabrication process.
摘要翻译：提供一种非易失性存储器件及其制造方法。形成第一栅极间绝缘层，以在单元阵列区域中的控制栅极电极和浮动栅极电极之间插入。形成第二栅极间绝缘层，以在外围电路区域中的栅电极和伪栅电极之间插入。所述第二栅极间绝缘层的厚度大于所述浮置栅电极的顶面上的所述第一栅极间绝缘层的厚度。通过减小浮置栅极图案的侧壁上的第一栅极间绝缘层的厚度与栅极电极图案上的第二栅极间绝缘层的厚度之间的差异，根据本发明，对衬底的任何蚀刻损伤在制造过程中可以显着地减少或防止在外围电路区域中。

10. 发明申请

US20050023600A1 NAND-type flash memory devices and methods of fabricating the same 有权
标题翻译： NAND型闪存器件及其制造方法
公开(公告)号：US20050023600A1
公开(公告)日：2005-02-03
申请号：US10921656
申请日：2004-08-19
申请人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
发明人： Kwang-Shik Shin , Kyu-Charn Park , Heung-Kwun Oh , Sung-Hoi Hur , Sang-Bin Song , Jung-Dal Choi
IPC分类号： H01L21/768 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788
CPC分类号： H01L27/11521 , H01L21/76802 , H01L27/115 , H01L27/11524
摘要： NAND-type flash memory devices and methods of fabricating the same are provided. The NAND-type flash memory device includes a plurality of isolation layers running parallel with each other, which are formed at predetermined regions of a semiconductor substrate. This device also includes a string selection line pattern, a plurality of word line patterns and a ground selection line pattern which cross over the isolation layers and active regions between the isolation layers. Source regions are formed in the active regions adjacent to the ground selection line patterns and opposite the string selection line pattern. The source regions and the isolation layers between the source regions are covered with a common source line running parallel with the ground selection line pattern.
摘要翻译：提供了NAND型闪存器件及其制造方法。 NAND型闪速存储器件包括彼此平行延伸的多个隔离层，它们形成在半导体衬底的预定区域。该装置还包括串联选择线图案，多个字线图案和跨越隔离层和隔离层之间的有源区域的接地选择线图案。源极区域形成在与地选择线图案相邻的有源区域中并且与串选择线图案相反。源极区域和源极区域之间的隔离层被与地选择线图案平行延伸的公共源极线覆盖。

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