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1. 发明授权

US07545651B2 Memory module with a predetermined arrangement of pins 有权
标题翻译：具有预定布置引脚的存储器模块
公开(公告)号：US07545651B2
公开(公告)日：2009-06-09
申请号：US11108245
申请日：2005-04-18
申请人： June E. Goodwin , Michael C. Day , Brian M. Johnson , John A. Nerl , Richard A. Schumacher , Vicki L. Smith
发明人： June E. Goodwin , Michael C. Day , Brian M. Johnson , John A. Nerl , Richard A. Schumacher , Vicki L. Smith
IPC分类号： H05K1/18
CPC分类号： G11C5/14 , G11C5/04 , H05K1/0219 , H05K1/0231 , H05K1/0263 , H05K1/117 , H05K2201/09145
摘要： A memory module according to one implementation includes a support substrate, plural memory devices mounted on the support substrate, and pins having a predetermined arrangement on the support substrate, the pins comprising signal pins connected to the memory devices, power pins, and ground pins. In the predetermined arrangement of pins, each signal pin uses a ground pin as a reference, and each power pin is adjacent a ground pin for reduced impedance between the power pin and ground pin. In some implementations, some of the signal pins are associated with redundant pins.
摘要翻译：根据一个实施方式的存储器模块包括支撑衬底，安装在支撑衬底上的多个存储器件以及在支撑衬底上具有预定布置的销，所述引脚包括连接到存储器件，电源引脚和接地引脚的信号引脚。在引脚的预定布置中，每个信号引脚使用接地引脚作为参考，并且每个电源引脚与接地引脚相邻，以在电源引脚和接地引脚之间降低阻抗。在一些实现中，一些信号引脚与冗余引脚相关联。

2. 发明授权

US07212424B2 Double-high DIMM with dual registers and related methods 失效
标题翻译：双高DIMM双重寄存器和相关方法
公开(公告)号：US07212424B2
公开(公告)日：2007-05-01
申请号：US11085693
申请日：2005-03-21
申请人： Brian M. Johnson , John Nerl , Ronald J. Bellomlo , Michael C. Day , Vicki L. Smith , Richard A. Schumacher , Rajakrishnan Radjassamy , June E. Goodwin
发明人： Brian M. Johnson , John Nerl , Ronald J. Bellomlo , Michael C. Day , Vicki L. Smith , Richard A. Schumacher , Rajakrishnan Radjassamy , June E. Goodwin
IPC分类号： G11C5/06
CPC分类号： G11C5/04 , H05K1/181
摘要： One memory module includes a printed circuit board comprising an upper row of memory integrated circuits, a lower row of memory integrated circuits, and a first addressing register and a second addressing register, the first addressing register and a second addressing register each having at least one of address and control input routing primarily provided in a first layer, the first addressing register coupled to the upper row of memory integrated circuits and the second addressing register coupled to the lower row of memory integrated circuits.
摘要翻译：一个存储器模块包括印刷电路板，其包括上行的存储器集成电路，下一排存储器集成电路，以及第一寻址寄存器和第二寻址寄存器，第一寻址寄存器和第二寻址寄存器，每个具有至少一个主要提供在第一层中的地址和控制输入路由，第一寻址寄存器耦合到上行存储器集成电路，第二寻址寄存器耦合到下行存储器集成电路。

3. 发明授权

US06596948B1 Processor and power supply circuit 失效
标题翻译：处理器和电源电路
公开(公告)号：US06596948B1
公开(公告)日：2003-07-22
申请号：US09560794
申请日：2000-04-28
申请人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Lisa Heid Pallotti
发明人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Lisa Heid Pallotti
IPC分类号： H01R1204
CPC分类号： H05K1/0231 , H05K1/0262 , H05K1/113 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611
摘要： A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.
摘要翻译：高性能处理器组件电连接到电源，以便最小化与向处理器组件供电的电压变化相关联。处理器组件制造在多层印刷电路板上。电源通过并联和分离电源平面提供给印刷电路板上的组件。并联和分离电源平面减小电感并增加与其相关联的电容。减小的电感降低了由负载瞬态电流引起的电压变化。电容器通过多个通孔电连接到电源层，以进一步降低电感。

4. 发明授权

US07475175B2 Multi-processor module 失效
标题翻译：多处理器模块
公开(公告)号：US07475175B2
公开(公告)日：2009-01-06
申请号：US10800837
申请日：2004-03-15
申请人： David A. Klein , Christian L. Belady , Shaun L. Harris , Michael C. Day , Jeffrey P. Christenson , Brent A. Boudreaux , Stuart C. Haden , Eric Peterson , Jeffrey N. Metcalf , James S. Wells , Gary W. Williams , Paul A. Wirtzberger , Roy M. Zeighami , Greg Huff
发明人： David A. Klein , Christian L. Belady , Shaun L. Harris , Michael C. Day , Jeffrey P. Christenson , Brent A. Boudreaux , Stuart C. Haden , Eric Peterson , Jeffrey N. Metcalf , James S. Wells , Gary W. Williams , Paul A. Wirtzberger , Roy M. Zeighami , Greg Huff
IPC分类号： H01L23/34 , H01L23/12 , H05K7/20 , G06F13/00
CPC分类号： G06F15/0216 , G06F15/7864
摘要： An apparatus comprises a plurality of logically independent processors, a system bus, and a cache control and bus bridge device in communication with the plurality of processors such that the cache control and bus bridge device is logically interposed between the processors and the system bus, and wherein the processors and cache control and bus bridge device are disposed in a module form factor such that the apparatus is a drop-in replacement for a standard single processor module.
摘要翻译：一种装置包括多个逻辑上独立的处理器，系统总线以及与多个处理器通信的高速缓存控制和总线桥接器件，使得高速缓存控制和总线桥接器件被逻辑地插入在处理器和系统总线之间，以及其中所述处理器和高速缓存控制和总线桥接器件以模块形式被布置，使得所述设备是用于标准单处理器模块的插入式替换。

5. 发明授权

US08433626B1 Method, medium, and system for flipping a list 有权
标题翻译：用于翻转列表的方法，介质和系统
公开(公告)号：US08433626B1
公开(公告)日：2013-04-30
申请号：US12859311
申请日：2010-08-19
申请人： Michael D. McDaniel , Jeffrey T. Brownell , Homer G. Morgan, III , Brent Russell Smith , Wesley M. Turner , Michael C. Day
发明人： Michael D. McDaniel , Jeffrey T. Brownell , Homer G. Morgan, III , Brent Russell Smith , Wesley M. Turner , Michael C. Day
IPC分类号： G06Q30/00
CPC分类号： G06Q30/06
摘要： Disclosed is a system for transitioning between views in a network page. An application that is executed in at least one computing device encodes a network page for rendering in a client, the network page including a region, and the region being configured for the rendering of at least two views. The network page is encoded to depict a transition between the two views. A first one of the views depicts at least one mechanism to add a depicted item in the network page to a list, and a second one of the views depicts at least a portion of the list. Once encoded, the network page is sent to the client.
摘要翻译：公开了一种用于在网页中的视图之间转换的系统。在至少一个计算设备中执行的应用程序对网络页面进行编码，以在客户机中呈现，网络页面包括区域，并且该区域被配置用于呈现至少两个视图。网络页面被编码以描绘两个视图之间的转换。视图中的第一个描述了至少一个机制，用于将网络页面中描绘的项目添加到列表中，并且第二个视图描绘了列表的至少一部分。一旦编码，网络页面被发送到客户端。

6. 发明授权

US06452789B1 Packaging architecture for 32 processor server 有权
标题翻译： 32处理器服务器的包装架构
公开(公告)号：US06452789B1
公开(公告)日：2002-09-17
申请号：US09562593
申请日：2000-04-29
申请人： Lisa Heid Pallotti , Eric C. Peterson , Christian L Belady , Terrel L. Morris , Michael C. Day
发明人： Lisa Heid Pallotti , Eric C. Peterson , Christian L Belady , Terrel L. Morris , Michael C. Day
IPC分类号： G06F1200
CPC分类号： G06F15/16
摘要： The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.
摘要翻译：本发明的系统使用背板来互连多个模块化单元板。每个单元板包括多个处理器，处理器控制器芯片，存储器子系统和电源子系统。处理器控制器芯片管理单元板上的组件之间的通信。机械子组件为电池板提供支撑，以及用于冷却的通风通道。控制器芯片连接到背板的一侧，而单元板连接到另一侧。控制器芯片管理单元板到单元板通信，以及背板和计算机系统之间的通信。单元板布置成背靠背对，其中最外面的单元板具有其组件延伸超出背板的高度。这允许相邻电池板的前面与前面之间的间隔增加。

7. 发明授权

US06818835B2 Processor and power supply circuit 有权
标题翻译：处理器和电源电路
公开(公告)号：US06818835B2
公开(公告)日：2004-11-16
申请号：US10420572
申请日：2003-04-22
申请人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Christian L Belady , Lisa Heid Pallotti , Paul T. Artman , Eric C. Peterson
发明人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Christian L Belady , Lisa Heid Pallotti , Paul T. Artman , Eric C. Peterson
IPC分类号： H05K103
CPC分类号： H05K1/0231 , H05K1/0262 , H05K1/113 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611
摘要： A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.
摘要翻译：本文公开了包括多个电路板的电路。电路的实施例可以包括第一和第二印刷电路板。第一印刷电路板可包括第一和第二导电平面。第一导电平面具有第一形状，第二导电平面具有第二形状，其中第一形状基本上类似于第二形状。第一导电平面位于第二导电平面附近，其中第一导电平面平行于第二导电平面并与第二导电平面对准。第二印刷电路板连接到第一印刷电路板。

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