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1. 发明授权

US06211028B1 Twin current bipolar device with hi-lo base profile 有权
标题翻译：双电流双极型器件，具有Hi-lo基座型材
公开(公告)号：US06211028B1
公开(公告)日：2001-04-03
申请号：US09245560
申请日：1999-02-05
申请人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/732
摘要： A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.
摘要翻译：描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

2. 发明授权

US06747336B2 Twin current bipolar device with hi-lo base profile 有权
标题翻译：双电流双极型器件，具有Hi-lo基座型材
公开(公告)号：US06747336B2
公开(公告)日：2004-06-08
申请号：US09804389
申请日：2001-03-13
申请人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/732
摘要： A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.
摘要翻译：描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

3. 发明授权

US06569730B2 High voltage transistor using P+ buried layer 有权
公开(公告)号：US06569730B2
公开(公告)日：2003-05-27
申请号：US10091990
申请日：2002-03-06
申请人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
IPC分类号： H01L218249
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

4. 发明授权

US06423590B2 High voltage transistor using P+ buried layer 有权
标题翻译：高压晶体管采用P +掩埋层
公开(公告)号：US06423590B2
公开(公告)日：2002-07-23
申请号：US09846538
申请日：2001-05-02
申请人： Jun-Lin Tsai , Ruey-Hsin Lin , Jei-Feng Hwang , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsin Lin , Jei-Feng Hwang , Kuo-Chio Liu
IPC分类号： H01L2100
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
摘要翻译：公开了一种用于高电压双极晶体管的新设计。代替埋置的子集电极（在NPN器件中将为N +），使用掩埋的P +层。该P +层的存在导致其本身和双极基底之间的夹断。这样可以实现更高的击穿电压。特别地，该装置不会在作为常规装置的弱点的基极 - 集电极结的底部分解。对该装置的制造方法进行说明。这个新工艺的一个特点是在P +层上生长的N型外延层只是传统器件中其对应厚度的大约一半。该工艺与传统的BiCMOS工艺完全兼容，成本较低。

5. 发明授权

US06245609B1 High voltage transistor using P+ buried layer 有权
公开(公告)号：US06245609B1
公开(公告)日：2001-06-12
申请号：US09405060
申请日：1999-09-27
申请人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
IPC分类号： H01L2100
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

6. 发明授权

US6162695A Field ring to improve the breakdown voltage for a high voltage bipolar device 有权
标题翻译：场环提高高压双极器件的击穿电压
公开(公告)号：US6162695A
公开(公告)日：2000-12-19
申请号：US376428
申请日：1999-08-18
申请人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Kuo-Chio Liu
发明人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Kuo-Chio Liu
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/06 , H01L29/08 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0619 , H01L29/0821
摘要： A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and located between a base and collector region. The use of the field ring results in an increase in collector-emitter breakdown voltage, as a result of the reduction in local dopant concentration in the N well region. This phenomena, the reduction the local dopant concentration in the N well region, in the vicinity of the field ring region, allows a higher N well dopant concentration to be used, resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated without the field ring regions, and thus with a lower N well dopant concentration.
摘要翻译：已经开发了用于制造具有同时形成的CMOS器件的共享多个工艺步骤的掩埋层夹持集电极双极（BPCB）器件的方法。 BPCB器件制造序列特征在于使用场环区域，放置在N阱区域中，并且位于基极和集电极区域之间。作为N阱区域中局部掺杂剂浓度降低的结果，使用场环导致集电极 - 发射极击穿电压的增加。在场环区域附近，N阱区域中的局部掺杂剂浓度的降低允许使用更高的N阱掺杂剂浓度，导致BPCB器件的频率响应（Ft）增加，当与没有场环区域制造的对应物相比，并且因此具有较低的N阱掺杂剂浓度时。

7. 发明授权

US07250344B2 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 有权
标题翻译：为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法
公开(公告)号：US07250344B2
公开(公告)日：2007-07-31
申请号：US11272260
申请日：2005-11-10
申请人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
发明人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
IPC分类号： H01L21/336
CPC分类号： H01L21/76232 , H01L21/763
摘要： A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.
摘要翻译：提供了一种形成用于半导体器件的浅沟槽 - 深沟槽隔离的方法。

8. 发明授权

US6165861A Integrated circuit polysilicon resistor having a silicide extension to achieve 100% metal shielding from hydrogen intrusion 有权
标题翻译：具有硅化物延伸的集成电路多晶硅电阻器，以实现100％金属屏蔽氢侵入
公开(公告)号：US6165861A
公开(公告)日：2000-12-26
申请号：US152348
申请日：1998-09-14
申请人： Ruey-Hsin Liu , Jun-Lin Tsai , Yung-Lung Hsu
发明人： Ruey-Hsin Liu , Jun-Lin Tsai , Yung-Lung Hsu
IPC分类号： H01L21/02 , H01L27/08 , H01L21/20
CPC分类号： H01L28/20 , H01L27/0802
摘要： A stable, high-value polysilicon resistor is achieved by using a silicide layer that prevents diffusion of hydrogen into the resistor. The resistor can also be integrated into a salicide process for making FETs without increasing process complexity. A polysilicon layer with a cap oxide is patterned to form FET gate electrodes and the polysilicon resistor. The lightly doped source/drains, insulating sidewall spacers, and source/drain contacts are formed for the FETs. The cap oxide is patterned to expose one end of the resistor, and the cap oxide is removed from the gate electrodes. A refractory metal is deposited and annealed to form the salicide FETs and concurrently to form a silicide on the end of the resistor. The unreacted metal is etched. An interlevel dielectric layer is deposited and contact holes with metal plugs are formed to both ends of the resistor. A metal is deposited to form the first level of metal interconnections, which also provides contacts to both ends of the resistor. The metal is also patterned to form a metal shield over the resistor to prevent hydrogen diffusion into the resistor. In this invention the spacing between the metal portions contacting the ends of the resistor is aligned over the silicide on the resistor to provide 100% shielding from hydrogen diffusion into the resistor.
摘要翻译：通过使用防止氢进入电阻器的硅化物层来实现稳定的高价值多晶硅电阻器。电阻器也可以集成到自对准硅化物工艺中，用于制造FET而不增加工艺复杂性。图案化具有帽氧化物的多晶硅层以形成FET栅电极和多晶硅电阻器。形成了用于FET的轻掺杂源极/漏极，绝缘侧壁间隔物和源极/漏极接触。盖帽氧化物被图案化以暴露电阻器的一端，并且帽状氧化物从栅电极移除。沉积和退火难熔金属以形成硅化物FET并同时在电阻器的末端形成硅化物。未反应的金属被蚀刻。沉积层间电介质层，并且在电阻器的两端形成与金属插塞的接触孔。沉积金属以形成第一级金属互连，其也提供与电阻器两端的接触。金属也被图案化以在电阻器上形成金属屏蔽，以防止氢扩散到电阻器中。在本发明中，接触电阻器端部的金属部分之间的间隔在电阻器上的硅化物上排列，以提供100％的阻挡氢扩散到电阻器中的屏蔽。

9. 发明申请

US20060063349A1 Method of forming a shallow trench-deep trench isolation region for a BiCMOS/CMOS technology 有权
标题翻译：为BiCMOS / CMOS技术形成浅沟槽深沟槽隔离区域的方法
公开(公告)号：US20060063349A1
公开(公告)日：2006-03-23
申请号：US11272260
申请日：2005-11-10
申请人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
发明人： Kuan-Lun Chang , Ruey-Hsin Liu , Tsyr-Shyang Liou , Chih-Min Chiang , Jun-Lin Tsai
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/763
摘要： A method of forming a shallow trench-deep trench isolation for a semiconductor device is provided.
摘要翻译：提供了一种形成用于半导体器件的浅沟槽 - 深沟槽隔离的方法。

10. 发明授权

US06242313B1 Use of polysilicon field plates to improve high voltage bipolar device breakdown voltage 有权
标题翻译：使用多晶硅场板来改善高压双极器件击穿电压
公开(公告)号：US06242313B1
公开(公告)日：2001-06-05
申请号：US09389891
申请日：1999-09-03
申请人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Jyh-Min Jiang
发明人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Jyh-Min Jiang
IPC分类号： H01L21331
CPC分类号： H01L29/404 , H01L21/765 , H01L21/8249 , H01L29/66272
摘要： A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of polysilicon field plates,. placed on field oxide regions, in an area of an N well region in which the field oxide regions are located between subsequent P type, base and N type, collector regions. The use of the polysilicon field plates results in an increase in collector—emitter breakdown voltage, as a result of a reduction in the electric field at the surface underlying the polysilicon field plates. The ability to increase collector —emitter breakdowns, via use of only polysilicon field plates, allows the use of higher N well dopant concentrations, thus resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated with the lower N well dopant concentrations, where the lower N well dopant concentration is needed to achieve the desired, increased collector emitter breakdowns.
摘要翻译：已经开发了用于制造具有同时形成的CMOS器件的共享多个工艺步骤的掩埋层夹持集电极双极（BPCB）器件的方法。 BPCB器件制造序列的特点是使用多晶硅场板。放置在场氧化物区域中，其中场氧化物区域位于其间的P型，基极和N型集电极区域的N阱区域的区域中。多晶硅场板的使用导致集电极 - 发射极击穿电压的增加，这是由于多晶硅场板下面的电场的电场减少的结果。通过仅使用多晶硅场板来增加集电极 - 发射体击穿的能力允许使用更高的N阱掺杂剂浓度，从而导致BPCB器件的频率响应（Ft）增加，与使用较低的N阱掺杂剂浓度，其中需要较低的N阱掺杂剂浓度以实现期望的增加的集电极发射极击穿。

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