专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US6162695A Field ring to improve the breakdown voltage for a high voltage bipolar device 有权
标题翻译：场环提高高压双极器件的击穿电压
公开(公告)号：US6162695A
公开(公告)日：2000-12-19
申请号：US376428
申请日：1999-08-18
申请人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Kuo-Chio Liu
发明人： Jei-Feng Hwang , Jun-Lin Tsai , Ruey-Hsin Liou , Kuo-Chio Liu
IPC分类号： H01L21/331 , H01L21/8249 , H01L29/06 , H01L29/08 , H01L21/8222
CPC分类号： H01L29/66272 , H01L21/8249 , H01L29/0619 , H01L29/0821
摘要： A method for fabricating a buried layer pinched collector bipolar, (BPCB), device, sharing several process steps with simultaneously formed CMOS devices, has been developed. The BPCB device fabrication sequence features the use of field ring regions, placed in an N well region, and located between a base and collector region. The use of the field ring results in an increase in collector-emitter breakdown voltage, as a result of the reduction in local dopant concentration in the N well region. This phenomena, the reduction the local dopant concentration in the N well region, in the vicinity of the field ring region, allows a higher N well dopant concentration to be used, resulting in increased frequency responses, (Ft), of the BPCB device, when compared to counterparts fabricated without the field ring regions, and thus with a lower N well dopant concentration.
摘要翻译：已经开发了用于制造具有同时形成的CMOS器件的共享多个工艺步骤的掩埋层夹持集电极双极（BPCB）器件的方法。 BPCB器件制造序列特征在于使用场环区域，放置在N阱区域中，并且位于基极和集电极区域之间。作为N阱区域中局部掺杂剂浓度降低的结果，使用场环导致集电极 - 发射极击穿电压的增加。在场环区域附近，N阱区域中的局部掺杂剂浓度的降低允许使用更高的N阱掺杂剂浓度，导致BPCB器件的频率响应（Ft）增加，当与没有场环区域制造的对应物相比，并且因此具有较低的N阱掺杂剂浓度时。

2. 发明授权

US06569730B2 High voltage transistor using P+ buried layer 有权
公开(公告)号：US06569730B2
公开(公告)日：2003-05-27
申请号：US10091990
申请日：2002-03-06
申请人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
IPC分类号： H01L218249
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

3. 发明授权

US06423590B2 High voltage transistor using P+ buried layer 有权
标题翻译：高压晶体管采用P +掩埋层
公开(公告)号：US06423590B2
公开(公告)日：2002-07-23
申请号：US09846538
申请日：2001-05-02
申请人： Jun-Lin Tsai , Ruey-Hsin Lin , Jei-Feng Hwang , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsin Lin , Jei-Feng Hwang , Kuo-Chio Liu
IPC分类号： H01L2100
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.
摘要翻译：公开了一种用于高电压双极晶体管的新设计。代替埋置的子集电极（在NPN器件中将为N +），使用掩埋的P +层。该P +层的存在导致其本身和双极基底之间的夹断。这样可以实现更高的击穿电压。特别地，该装置不会在作为常规装置的弱点的基极 - 集电极结的底部分解。对该装置的制造方法进行说明。这个新工艺的一个特点是在P +层上生长的N型外延层只是传统器件中其对应厚度的大约一半。该工艺与传统的BiCMOS工艺完全兼容，成本较低。

4. 发明授权

US06245609B1 High voltage transistor using P+ buried layer 有权
公开(公告)号：US06245609B1
公开(公告)日：2001-06-12
申请号：US09405060
申请日：1999-09-27
申请人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsin Liu , Jei-Feng Hwang , Kuo-Chio Liu
IPC分类号： H01L2100
CPC分类号： H01L29/66272 , H01L29/0821 , H01L29/7322
摘要： A new design for a high voltage bipolar transistor is disclosed. Instead of a buried subcollector (which would be N+ in an NPN device), a buried P+ layer is used. The presence of this P+ layer results in pinch-off between itself and the bipolar base. This allows much higher breakdown voltages to be achieved. In particular, the device will not break down at the bottom of the base-collector junction which is the weak spot for conventional devices. A process for manufacturing this device is described. A particular feature of this new process is that the N type epitaxial layer that is grown over the P+ layer is only about half the thickness of its counterpart in the conventional device. The process is fully compatible with conventional BiCMOS processes and has lower cost.

5. 发明授权

US06211028B1 Twin current bipolar device with hi-lo base profile 有权
标题翻译：双电流双极型器件，具有Hi-lo基座型材
公开(公告)号：US06211028B1
公开(公告)日：2001-04-03
申请号：US09245560
申请日：1999-02-05
申请人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
IPC分类号： H01L21331
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/732
摘要： A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.
摘要翻译：描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

6. 发明授权

US06747336B2 Twin current bipolar device with hi-lo base profile 有权
标题翻译：双电流双极型器件，具有Hi-lo基座型材
公开(公告)号：US06747336B2
公开(公告)日：2004-06-08
申请号：US09804389
申请日：2001-03-13
申请人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
发明人： Jun-Lin Tsai , Ruey-Hsing Liu , Chiou-Shian Peng , Kuo-Chio Liu
IPC分类号： H01L27082
CPC分类号： H01L29/66272 , H01L29/1004 , H01L29/732
摘要： A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.
摘要翻译：描述了一种双极性晶体管，其I-V曲线使得其工作在两个区域中，一个具有低增益和低功耗，另一个具有较高的增益和更好的电流驱动能力。所述晶体管具有由两个子区域构成的基极区域，最靠近发射极的区域的电阻率大约低于第二区域（与集电极接口）的数量级。本发明的关键特征是最靠近集电极的区域是非常均匀的掺杂的，即没有梯度或内置的场存在。为了制造这样的区域，使用外延生长以及硼掺杂，而不是诸如离子注入和/或扩散的更常规的技术。

7. 发明申请

US20110084391A1 Reducing Device Mismatch by Adjusting Titanium Formation 审中-公开
标题翻译：通过调整钛形成减少装置不匹配
公开(公告)号：US20110084391A1
公开(公告)日：2011-04-14
申请号：US12842753
申请日：2010-07-23
申请人： Shyh-Wei Cheng , Pin-Shyne Chin , Kuo-Chio Liu , Che-Jung Chu , Ming-Chang Hsieh , Hung-Lin Chen , Tian Sheng Lin
发明人： Shyh-Wei Cheng , Pin-Shyne Chin , Kuo-Chio Liu , Che-Jung Chu , Ming-Chang Hsieh , Hung-Lin Chen , Tian Sheng Lin
IPC分类号： H01L23/532
CPC分类号： H01L24/05 , H01L24/03 , H01L24/13 , H01L2224/0231 , H01L2224/02313 , H01L2224/0233 , H01L2224/0239 , H01L2224/0401 , H01L2224/05006 , H01L2224/05022 , H01L2224/05568 , H01L2224/05572 , H01L2224/05599 , H01L2224/13006 , H01L2224/13023 , H01L2924/00014 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/014 , H01L2924/04941 , H01L2924/14 , H01L2224/05552
摘要： An integrated circuit structure includes a semiconductor substrate; a first titanium layer over the semiconductor substrate, wherein the first titanium layer has a first thickness less than 130 Å; a first titanium nitride layer over and contacting the first titanium layer; and an aluminum-containing layer over and contacting the first titanium nitride layer.
摘要翻译：集成电路结构包括半导体衬底; 半导体衬底上的第一钛层，其中第一钛层具有小于130的第一厚度; 在第一钛层上方并与第一钛层接触的第一氮化钛层; 以及与第一氮化钛层接触的含铝层。

8. 发明授权

US06358781B1 Uniform current distribution SCR device for high voltage ESD protection 有权
公开(公告)号：US06358781B1
公开(公告)日：2002-03-19
申请号：US09607043
申请日：2000-06-30
申请人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
IPC分类号： H01L21332
CPC分类号： H01L27/0266
摘要： NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.

9. 发明申请

US20050194647A1 High voltage device embedded non-volatile memory cell and fabrication method 有权
标题翻译：高压器件嵌入式非易失性存储单元及制造方法
公开(公告)号：US20050194647A1
公开(公告)日：2005-09-08
申请号：US10793972
申请日：2004-03-05
申请人： Hung-Chih Tsai , Chien-Chih Chou , Ying-Ting Chang , Che-Jung Chu , Kuo-Chio Liu
发明人： Hung-Chih Tsai , Chien-Chih Chou , Ying-Ting Chang , Che-Jung Chu , Kuo-Chio Liu
IPC分类号： H01L31/113
CPC分类号： H01L29/7835 , H01L29/1045 , H01L29/42368 , H01L29/456
摘要： A high voltage PMOS device having an improved breakdown voltage is achieved. An asymmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate and source and drain regions within the substrate on either side and adjacent to the gate electrode wherein the source region is encompassed by an n-well. A symmetrical high voltage integrated circuit structure comprises a gate electrode on a substrate, source and drain regions within the substrate on either side and adjacent to the gate electrode, and an n-well in the substrate underlying the gate electrode. The n-well in both structures shifts the breakdown point from the silicon surface to the bottom of the source or drain regions.
摘要翻译：实现了具有改善的击穿电压的高电压PMOS器件。不对称的高压集成电路结构包括衬底上的栅极电极和位于栅极电极的任一侧和邻近的衬底内的源极和漏极区域，其中源极区域被n阱包围。对称的高压集成电路结构包括衬底上的栅极电极，位于栅极电极的任一侧和邻近衬底内的源极和漏极区域以及位于栅极电极下方的衬底中的n-阱。两个结构中的n阱将击穿点从硅表面移动到源极或漏极区域的底部。

10. 发明授权

US06459127B1 Uniform current distribution SCR device for high voltage ESD protection 有权
标题翻译：均匀电流分配用于高压ESD保护的SCR器件
公开(公告)号：US06459127B1
公开(公告)日：2002-10-01
申请号：US10043793
申请日：2002-01-14
申请人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
发明人： Jian-Hsing Lee , Kuo-Chio Liu , Bing-Lung Liao , Jiaw-Ren Shih
IPC分类号： H01L2362
CPC分类号： H01L27/0266
摘要： NMOS transistors for a high voltage process are protected from electrostatic discharge (ESD) by parasitic SCRs, where the two NMOS transistors and the two SCRs are designed to be in a completely symmetrical arrangement so that the currents in the components of the SCRs are completely uniform. This symmetry is achieved by adding a p+ diffusion to the source of one of the NMOS transistors. The added p+ diffusion guarantees that the resistance seen by both SCRs is identical. This insures even current distribution between both SCRs and thereby improves the high voltage characteristics of the ESD device.
摘要翻译：用于高电压工艺的NMOS晶体管通过寄生SCR防止静电放电（ESD），其中两个NMOS晶体管和两个SCR被设计为完全对称的布置，使得SCR的部件中的电流是完全均匀的。该对称性是通过向NMOS晶体管之一的源极添加p +扩散来实现的。添加的p +扩散保证两个SCR看到的电阻是相同的。这确保了两个SCR之间的均匀电流分布，从而改善了ESD器件的高电压特性。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式