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1. 发明授权

US08482963B1 Integrated circuits with asymmetric and stacked transistors 有权
标题翻译：具有不对称和堆叠晶体管的集成电路
公开(公告)号：US08482963B1
公开(公告)日：2013-07-09
申请号：US12629831
申请日：2009-12-02
申请人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
发明人： Jun Liu , Yanzhong Xu , Shankar Sinha , Shih-Lin S. Lee , Jeffrey Xiaoqi Tung , Albert Ratnakumar , Qi Xiang , Irfan Rahim , Andy L. Lee , Jeffrey T. Watt , Srinivas Perisetty
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.
摘要翻译：不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。两个晶体管的栅极也连接在一起。两个晶体管可以具有不同的阈值电压。位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。不对称晶体管也可用于存储器单元中以减少泄漏。

2. 发明授权

US08218353B1 Memory element circuitry with stressed transistors 有权
标题翻译：具有应力晶体管的存储元件电路
公开(公告)号：US08218353B1
公开(公告)日：2012-07-10
申请号：US12561236
申请日：2009-09-16
申请人： Jun Liu , Shankar Sinha , Qi Xiang , Yow-Juang Liu
发明人： Jun Liu , Shankar Sinha , Qi Xiang , Yow-Juang Liu
IPC分类号： G11C11/00
CPC分类号： G11C11/412
摘要： Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.
摘要翻译：提供具有存储元件的集成电路。存储器元件可以被布置在存储器块中。存储器块可以包括存储数据的交叉耦合的反相器。存储的数据可用于编程传输晶体管。存储器块中的晶体管可能受到压力。根据所使用的应力诱导层的类型，可以将内部的拉伸应力或压应力内置到晶体管中。受压的晶体管可能有助于提高存储器块的布线速度。可以使用双栅极氧化工艺来实施受压晶体管。

3. 发明申请

US20120311401A1 MULTIPORT MEMORY ELEMENT CIRCUITRY 有权
标题翻译：多媒体存储元件电路
公开(公告)号：US20120311401A1
公开(公告)日：2012-12-06
申请号：US13149249
申请日：2011-05-31
申请人： Shih-Lin S. Lee , Peter J. McElheny , Preminder Singh , Shankar Sinha
发明人： Shih-Lin S. Lee , Peter J. McElheny , Preminder Singh , Shankar Sinha
IPC分类号： G11C7/00 , G06F11/10 , H03M13/05
CPC分类号： G11C7/00 , G06F12/1425 , G11C8/16 , G11C2029/0411
摘要： Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.
摘要翻译：可以提供具有多端口存储器元件的集成电路。多端口存储元件可以包括锁存电路，第一组地址晶体管和第二组地址晶体管。锁存电路可以包括交叉耦合的反相器，每个反相器包括上拉晶体管和下拉晶体管。第一组地址晶体管可以将锁存电路耦合到写入端口，而第二组地址晶体管可以将锁存电路耦合到读取端口。下拉晶体管和第二组地址晶体管可以具有由控制信号控制的体偏置端子。在数据加载操作期间，控制信号可以临时升高以削弱下拉晶体管和第二组地址晶体管，以改善多端口存储器元件的写入裕度。

4. 发明授权

US08755218B2 Multiport memory element circuitry 有权
标题翻译：多端口存储元件电路
公开(公告)号：US08755218B2
公开(公告)日：2014-06-17
申请号：US13149249
申请日：2011-05-31
申请人： Shih-Lin S. Lee , Peter J. McElheny , Preminder Singh , Shankar Sinha
发明人： Shih-Lin S. Lee , Peter J. McElheny , Preminder Singh , Shankar Sinha
IPC分类号： G11C11/00
CPC分类号： G11C7/00 , G06F12/1425 , G11C8/16 , G11C2029/0411
摘要： Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.
摘要翻译：可以提供具有多端口存储器元件的集成电路。多端口存储元件可以包括锁存电路，第一组地址晶体管和第二组地址晶体管。锁存电路可以包括交叉耦合的反相器，每个反相器包括上拉晶体管和下拉晶体管。第一组地址晶体管可以将锁存电路耦合到写入端口，而第二组地址晶体管可以将锁存电路耦合到读取端口。下拉晶体管和第二组地址晶体管可以具有由控制信号控制的体偏置端子。在数据加载操作期间，控制信号可以临时升高以削弱下拉晶体管和第二组地址晶体管，以改善多端口存储器元件的写入裕度。

5. 发明授权

US08638594B1 Integrated circuits with asymmetric transistors 有权
标题翻译：具有不对称晶体管的集成电路
公开(公告)号：US08638594B1
公开(公告)日：2014-01-28
申请号：US13110823
申请日：2011-05-18
申请人： Shankar Sinha , Shih-Lin S. Lee , Peter J. McElheny
发明人： Shankar Sinha , Shih-Lin S. Lee , Peter J. McElheny
IPC分类号： G11C11/00 , H01L21/02
CPC分类号： H01L27/1052 , G11C11/412 , H01L27/1104
摘要： Integrated circuits with memory elements are provided. A memory element may include a storage circuit coupled to data lines through access transistors. Access transistors may be used to read data from and write data into the storage circuit. An access transistor may have asymmetric source-drain resistances. The access transistor may have a first source-drain that is coupled to a data line and a second source-drain that is coupled to the storage circuit. The second source-drain may have a contact resistance that is greater than the contact resistance associated with the first source-drain. Access transistors with asymmetric source-drain resistances may have a first drive strength when passing a low signal and a second drive strength when passing a high signal to the storage circuit. The second drive strength may be less than the first drive strength. Access transistors with asymmetric drive strengths may be used to improve memory read/write performance.
摘要翻译：提供具有存储元件的集成电路。存储元件可以包括通过存取晶体管耦合到数据线的存储电路。存取晶体管可用于从存储电路读取数据并将数据写入存储电路。存取晶体管可以具有不对称的源极 - 漏极电阻。存取晶体管可以具有耦合到数据线的第一源极 - 漏极和耦合到存储电路的第二源极 - 漏极。第二源极 - 漏极可以具有大于与第一源极 - 漏极相关联的接触电阻的接触电阻。具有不对称源极 - 漏极电阻的存取晶体管在通过高信号到存储电路时通过低信号和第二驱动强度时可具有第一驱动强度。第二驱动强度可能小于第一驱动强度。具有非对称驱动强度的存取晶体管可用于提高存储器读/写性能。

6. 发明授权

US08861283B1 Systems and methods for reducing leakage current in memory arrays 有权
标题翻译：减少存储器阵列泄漏电流的系统和方法
公开(公告)号：US08861283B1
公开(公告)日：2014-10-14
申请号：US13605428
申请日：2012-09-06
申请人： Brian Yung Fun Wong , Shankar Sinha , Shih-Lin S. Lee , Abhishek B. Sharma
发明人： Brian Yung Fun Wong , Shankar Sinha , Shih-Lin S. Lee , Abhishek B. Sharma
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C11/419
摘要： Disclosed are apparatus and devices for programming and operating a programmable memory array portion coupled with a leakage reduction circuit. At the leakage reduction circuit, a frame bias signal that indicates a majority state of the memory array portion can be received. During idle states of the programmable memory array portion, at least one shared bit line of the memory array portion can be selectively biased based on the received frame bias signal. In one aspect, a first one of two bit lines is biased to a first state, while the second one of the two bits lines is biased to a second state that is opposite the first state. In a further aspect, the first state is a same state as the majority state of the memory array portion.
摘要翻译：公开了用于编程和操作与泄漏减少电路耦合的可编程存储器阵列部分的装置和装置。在泄漏降低电路中，可以接收指示存储器阵列部分的多数状态的帧偏置信号。在可编程存储器阵列部分的空闲状态期间，存储器阵列部分的至少一个共享位线可以基于所接收的帧偏置信号被选择性地偏置。在一个方面，两个位线中的第一位被偏置到第一状态，而两个位线中的第二位被偏置到与第一状态相反的第二状态。在另一方面，第一状态是与存储器阵列部分的多数状态相同的状态。

7. 发明授权

US08619464B1 Static random-access memory having read circuitry with capacitive storage 有权
标题翻译：具有电容存储的读取电路的静态随机存取存储器
公开(公告)号：US08619464B1
公开(公告)日：2013-12-31
申请号：US13219537
申请日：2011-08-26
申请人： Shankar Sinha , Brian Wong , Shih-Lin S. Lee , Abhishek Sharma
发明人： Shankar Sinha , Brian Wong , Shih-Lin S. Lee , Abhishek Sharma
IPC分类号： G11C11/00
CPC分类号： G11C7/02 , G11C8/16 , G11C11/412 , G11C11/419 , H01L27/1104
摘要： Integrated circuits may have arrays of memory elements. Data may be loaded into the memory elements and read from the memory elements using data lines. Address lines may be used to apply address signals to write address transistors and read circuitry. A memory element may include a bistable storage element. Read circuitry may be coupled between the bistable storage element and a data line. The read circuitry may include a data storage node. A capacitor may be coupled between the data storage node and ground and may be used in storing preloaded data from the bistable storage element. The read circuitry may include a transistor that is coupled between the bistable storage element and the data storage node and a transistor that is coupled between the data storage node and the data line.
摘要翻译：集成电路可以具有存储元件阵列。数据可以被加载到存储器元件中并且使用数据线从存储器元件读取。地址线可以用于施加地址信号以写入地址晶体管和读取电路。存储元件可以包括双稳态存储元件。读取电路可以耦合在双稳态存储元件和数据线之间。所述读取电路可以包括数据存储节点。电容器可以耦合在数据存储节点和地之间，并且可以用于存储来自双稳态存储元件的预加载的数据。读取电路可以包括耦合在双稳态存储元件和数据存储节点之间的晶体管，以及耦合在数据存储节点和数据线之间的晶体管。

8. 发明授权

US07561457B2 Select transistor using buried bit line from core 有权
标题翻译：选择晶体管使用埋入位线从核心
公开(公告)号：US07561457B2
公开(公告)日：2009-07-14
申请号：US11465701
申请日：2006-08-18
申请人： Mark Randolph , Zhizheng Liu , Ashot Melik-Martirosian , Yi He , Shankar Sinha
发明人： Mark Randolph , Zhizheng Liu , Ashot Melik-Martirosian , Yi He , Shankar Sinha
IPC分类号： G11C17/00
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105 , H01L27/11519 , H01L27/11526 , H01L27/11531
摘要： A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.
摘要翻译：半导体器件包括核心存储器阵列和周边区域。核心存储器阵列区域包括一组存储器单元。外围区域包括一组选择晶体管。选择晶体管以与芯存储器阵列中的存储器单元基本相同的间距形成并具有基本上相同的沟道长度。

9. 发明授权

US08409952B2 Method of forming an electronic device including forming a charge storage element in a trench of a workpiece 有权
标题翻译：形成电子器件的方法，包括在工件的沟槽中形成电荷存储元件
公开(公告)号：US08409952B2
公开(公告)日：2013-04-02
申请号：US12102488
申请日：2008-04-14
申请人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
发明人： Suketu Arun Parikh , Olov B. Karlsson , Yun Sun , Shankar Sinha , Timothy Thurgate
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/26586 , H01L27/115 , H01L29/1041 , H01L29/66666 , H01L29/7827
摘要： A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.
摘要翻译：一种形成电子器件的方法，包括在包括衬底的工件中形成第一沟槽，所述第一沟槽具有侧壁和在所述侧壁之间延伸宽度的底表面，并且沿着所述侧壁和底部形成电荷存储层第一沟槽的表面。该方法还包括在第一沟槽的底表面下方的衬底内注入离子以形成植入区域并退火植入区域，其中在退火之后，植入区域延伸底表面的宽度并沿着侧壁的一部分。

10. 发明授权

US08148770B1 Memory device with buried bit line structure 有权
标题翻译：具有埋地位线结构的存储器件
公开(公告)号：US08148770B1
公开(公告)日：2012-04-03
申请号：US11165329
申请日：2005-06-24
申请人： Shankar Sinha , Timothy Thurgate
发明人： Shankar Sinha , Timothy Thurgate
IPC分类号： H01L29/792 , H01L23/52 , H01L29/40 , H01L27/088 , H01L21/70 , H01L23/48 , H01L21/82 , H01L21/336 , H01L21/76 , H01L21/44 , H01L29/788
CPC分类号： H01L29/792 , H01L29/78675 , H01L29/7881 , Y10S438/954
摘要： A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.
摘要翻译：存储器件包括多个存储器单元和耦合到一组存储器单元的位线结构。位线结构包括具有第一宽度的上部和具有第二宽度的下部，其中第一宽度小于第二宽度。

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