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1. 发明申请

US20110221475A1 LOGIC CIRCUIT 有权
标题翻译：逻辑电路
公开(公告)号：US20110221475A1
公开(公告)日：2011-09-15
申请号：US13116372
申请日：2011-05-26
申请人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
发明人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H03K19/0944 , H01L27/088
CPC分类号： H03K19/094 , H01L27/0883 , H01L27/1225 , H03K19/09407 , H03K19/09421 , H03K19/096
摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
摘要翻译：目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极。晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

2. 发明申请

US20100109708A1 LOGIC CIRCUIT 有权
标题翻译：逻辑电路
公开(公告)号：US20100109708A1
公开(公告)日：2010-05-06
申请号：US12605607
申请日：2009-10-26
申请人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
发明人： Jun KOYAMA , Kengo AKIMOTO , Masashi TSUBUKU
IPC分类号： H03K19/096 , H01L27/088
CPC分类号： H03K19/094 , H01L27/0883 , H01L27/1225 , H03K19/09407 , H03K19/09421 , H03K19/096
摘要： An object is to apply a transistor using an oxide semiconductor to a logic circuit including an enhancement transistor. The logic circuit includes a depletion transistor 101 and an enhancement transistor 102. The transistors 101 and 102 each include a gate electrode, a gate insulating layer, a first oxide semiconductor layer, a second oxide semiconductor layer, a source electrode, and a drain electrode. The transistor 102 includes a reduction prevention layer provided over a region in the first oxide semiconductor layer between the source electrode and the drain electrode.
摘要翻译：目的是将使用氧化物半导体的晶体管施加到包括增强晶体管的逻辑电路。逻辑电路包括耗尽晶体管101和增强晶体管102.晶体管101和102各自包括栅电极，栅极绝缘层，第一氧化物半导体层，第二氧化物半导体层，源电极和漏电极。晶体管102包括在源电极和漏极之间的第一氧化物半导体层中的区域上设置的还原防止层。

3. 发明申请

US20120299003A1 ANALOG CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译：模拟电路和半导体器件
公开(公告)号：US20120299003A1
公开(公告)日：2012-11-29
申请号：US13568186
申请日：2012-08-07
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Atsushi HIROSE , Masashi TSUBUKU , Kosei NODA
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Atsushi HIROSE , Masashi TSUBUKU , Kosei NODA
IPC分类号： H01L29/22 , H01L27/15 , H01L29/786
CPC分类号： H01L27/1225 , H01L21/823412 , H01L27/124 , H01L27/1255 , H01L27/156 , H01L27/3213 , H01L29/24 , H01L29/36 , H01L29/7869 , H01L29/78693 , H01L33/025 , H01L2924/0002 , H04M1/0266 , H04R1/02 , H01L2924/00
摘要： An object is to obtain a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range, using a thin film transistor in which an oxide semiconductor layer is used. An analog circuit is formed with the use of a thin film transistor including an oxide semiconductor which has a function as a channel formation layer, has a hydrogen concentration of 5×1019 atoms/cm3 or lower, and substantially functions as an insulator in the state where no electric field is generated. Thus, a semiconductor device having a high sensitivity in detecting signals and a wide dynamic range can be obtained.
摘要翻译：目的是获得使用其中使用氧化物半导体层的薄膜晶体管，在检测信号和宽动态范围中具有高灵敏度的半导体器件。使用具有作为沟道形成层的功能的氧化物半导体的薄膜晶体管形成模拟电路，其氢浓度为5×1019个原子/ cm3以下，并且在该状态下基本上起绝缘体的作用其中不产生电场。因此，可以获得在检测信号中具有高灵敏度和宽动态范围的半导体器件。

4. 发明申请

US20110090183A1 LIQUID CRYSTAL DISPLAY DEVICE AND ELECTRONIC DEVICE INCLUDING THE LIQUID CRYSTAL DISPLAY DEVICE 有权
标题翻译：液晶显示装置和包括液晶显示装置的电子装置
公开(公告)号：US20110090183A1
公开(公告)日：2011-04-21
申请号：US12901023
申请日：2010-10-08
申请人： Shunpei YAMAZAKI , Ryo ARASAWA , Jun KOYAMA , Masashi TSUBUKU , Kosei NODA
发明人： Shunpei YAMAZAKI , Ryo ARASAWA , Jun KOYAMA , Masashi TSUBUKU , Kosei NODA
IPC分类号： G09G5/00 , G09G3/36
CPC分类号： G09G3/3614 , G02F1/133553 , G02F1/13439 , G02F1/1368 , G02F2201/123 , G02F2202/10 , G09G3/3648 , G09G3/3677 , G09G2300/08 , G09G2310/0286 , G09G2310/08 , G09G2330/021 , H01L21/02164 , H01L21/02266 , H01L21/02565 , H01L21/02631 , H01L21/467 , H01L21/477 , H01L27/1225 , H01L27/1255 , H01L29/24 , H01L29/42356 , H01L29/45 , H01L29/66969 , H01L29/78648 , H01L29/7869
摘要： In a liquid crystal display device including a plurality of pixels in a display portion and configured to performed display in a plurality of frame periods, each of the frame periods includes a writing period and a holding period, and after an image signal is input to each of the plurality of pixels in the writing period, a transistor included in each of the plurality of pixels is turned off and the image signal is held for at least 30 seconds in the holding period. The pixel includes a semiconductor layer including an oxide semiconductor layer, and the oxide semiconductor layer has a carrier concentration of less than 1×1014/cm3.
摘要翻译：在包括显示部分中的多个像素并且被配置为在多个帧周期中进行显示的液晶显示装置中，每个帧周期包括写入周期和保持周期，并且在将图像信号输入到每个在所述写入周期中的所述多个像素中，包括在所述多个像素中的每一个中的晶体管被截止，并且所述图像信号在所述保持周期中保持至少30秒。像素包括具有氧化物半导体层的半导体层，氧化物半导体层的载流子浓度小于1×10 14 / cm 3。

5. 发明申请

US20110090184A1 LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US20110090184A1
公开(公告)日：2011-04-21
申请号：US12902670
申请日：2010-10-12
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Masashi TSUBUKU , Kosei NODA
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Masashi TSUBUKU , Kosei NODA
IPC分类号： G06F3/038 , H03K19/0175
CPC分类号： H01L27/1255 , G09G3/20 , G09G3/2092 , G09G3/3233 , G09G3/3291 , G09G3/36 , G09G3/3648 , G09G2300/0439 , G09G2300/08 , G09G2300/0842 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/08 , G11C19/184 , G11C19/28 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L29/7869 , H03K17/161 , H03K19/00315 , H03K19/096
摘要： To reduce a leakage current of a transistor so that malfunction of a logic circuit can be suppressed. The logic circuit includes a transistor which includes an oxide semiconductor layer having a function of a channel formation layer and in which an off current is 1×10−13 A or less per micrometer in channel width. A first signal, a second signal, and a third signal that is a clock signal are input as input signals. A fourth signal and a fifth signal whose voltage states are set in accordance with the first to third signals which have been input are output as output signals.
摘要翻译：为了减小晶体管的漏电流，可以抑制逻辑电路的故障。逻辑电路包括晶体管，其包括具有沟道形成层的功能的氧化物半导体层，并且其中截止电流在沟道宽度中为每微米1×10-13A或更小。作为时钟信号的第一信号，第二信号和第三信号被输入作为输入信号。作为输出信号输出第四信号和第五信号，其电压状态根据输入的第一至第三信号而被设定。

6. 发明申请

US20110089975A1 LOGIC CIRCUIT AND SEMICONDUCTOR DEVICE 有权
标题翻译：逻辑电路和半导体器件
公开(公告)号：US20110089975A1
公开(公告)日：2011-04-21
申请号：US12901057
申请日：2010-10-08
申请人： Shunpei YAMAZAKI , Jun KOYAMA , Masashi TSUBUKU , Kosei NODA
发明人： Shunpei YAMAZAKI , Jun KOYAMA , Masashi TSUBUKU , Kosei NODA
IPC分类号： H03K19/08 , H01L29/12
CPC分类号： H01L29/7869 , H01L22/34 , H01L27/0207 , H01L27/1225 , H01L29/78696 , H01L2924/0002 , H01L2924/00
摘要： A logic circuit includes a thin film transistor having a channel formation region formed using an oxide semiconductor, and a capacitor having terminals one of which is brought into a floating state by turning off the thin film transistor. The oxide semiconductor has a hydrogen concentration of 5×1019 (atoms/cm3) or less and thus substantially serves as an insulator in a state where an electric field is not generated. Therefore, off-state current of a thin film transistor can be reduced, leading to suppressing the leakage of electric charge stored in a capacitor, through the thin film transistor. Accordingly, a malfunction of the logic circuit can be prevented. Further, the excessive amount of current which flows in the logic circuit can be reduced through the reduction of off-state current of the thin film transistor, resulting in low power consumption of the logic circuit.
摘要翻译：逻辑电路包括具有使用氧化物半导体形成的沟道形成区域的薄膜晶体管，以及通过关闭薄膜晶体管而使端子中的一个成为浮置状态的电容器。氧化物半导体的氢浓度为5×1019（原子/ cm3）以下，因此在不产生电场的状态下基本上用作绝缘体。因此，可以减小薄膜晶体管的截止电流，从而通过薄膜晶体管抑制存储在电容器中的电荷的泄漏。因此，可以防止逻辑电路的故障。此外，可以通过减小薄膜晶体管的截止电流来降低在逻辑电路中流动的过量的电流，导致逻辑电路的低功耗。

7. 发明申请

US20130037884A1 NONVOLATILE MEMORY AND ELECTRONIC APPARATUS 失效
公开(公告)号：US20130037884A1
公开(公告)日：2013-02-14
申请号：US13549914
申请日：2012-07-16
申请人： Shunpei YAMAZAKI , Hisashi OHTANI , Jun KOYAMA , Takeshi FUKUNAGA
发明人： Shunpei YAMAZAKI , Hisashi OHTANI , Jun KOYAMA , Takeshi FUKUNAGA
IPC分类号： H01L29/786
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/115 , H01L27/1203 , H01L29/42324 , H01L29/78609 , H01L29/78675 , H01L29/7881
摘要： An active region, a source region, and a drain region are formed on a single crystal semiconductor substrate or a single crystal semiconductor thin film. Impurity regions called pinning regions are formed in striped form in the active region so as to reach both of the source region and the drain region. Regions interposed between the pinning regions serve as channel forming regions. A tunnel oxide film, a floating gate, a control gate, etc. are formed on the above structure. The impurity regions prevent a depletion layer from expanding from the source region toward the drain region.

8. 发明申请

US20130021239A1 DISPLAY DEVICE 有权
标题翻译：显示设备
公开(公告)号：US20130021239A1
公开(公告)日：2013-01-24
申请号：US13545768
申请日：2012-07-10
申请人： Jun KOYAMA , Hiroyuki MIYAKE , Hideaki SHISHIDO , Seiko INOUE , Kouhei TOYOTAKA , Koji KUSUNOKI , Hikaru HARADA , Makoto KANEYASU
发明人： Jun KOYAMA , Hiroyuki MIYAKE , Hideaki SHISHIDO , Seiko INOUE , Kouhei TOYOTAKA , Koji KUSUNOKI , Hikaru HARADA , Makoto KANEYASU
IPC分类号： G09G3/36 , G06F3/038 , G06F3/01
CPC分类号： H04N13/376 , H04N13/315 , H04N13/324 , H04N13/356 , H04N13/373
摘要： A display device includes a display panel including a plurality of pixels, a shutter panel including a driver circuit, a liquid crystal, and light-transmitting electrodes provided in a striped manner, and a positional data detector configured to detect a positional data of a viewer. The shutter panel is provided over a display surface side of the display panel, a width of one of the light-transmitting electrodes in the shutter panel is smaller than that of one of the plurality of pixels, and the driver circuit in the shutter panel is configured to selectively output signals for forming a parallax barrier to the light-transmitting electrodes. The parallax barrier is capable of changing its shape in accordance with the detected positional data.
摘要翻译：一种显示装置，包括：包括多个像素的显示面板;包括驱动电路的快门面板;液晶;以条纹方式设置的透光电极;以及位置数据检测器，被配置为检测观察者的位置数据。快门面板设置在显示面板的显示面侧，快门面板中的一个透光电极的宽度小于多个像素中的一个透光电极的宽度，而快门面板中的驱动电路为被配置为选择性地输出用于形成对透光电极的视差屏障的信号。视差屏障能够根据检测到的位置数据改变其形状。

9. 发明申请

US20120306728A1 Display Device, Driving Method Of The Same, and Electronic Device 有权
标题翻译：显示设备及其驱动方法和电子设备
公开(公告)号：US20120306728A1
公开(公告)日：2012-12-06
申请号：US13484489
申请日：2012-05-31
申请人： Jun KOYAMA , Shunpei YAMAZAKI
发明人： Jun KOYAMA , Shunpei YAMAZAKI
IPC分类号： G09G3/30
CPC分类号： G09G3/3216 , G09G3/3233 , G09G3/3266 , G09G3/3275 , G09G2300/0842 , G09G2310/0262 , G09G2310/061 , G09G2320/0223 , G09G2320/0233 , G09G2320/029 , G09G2320/041 , G09G2320/043
摘要： A display device suppresses the influence of variations of a current value supplied to a light emitting element caused by a temperature change. In particular, luminance variations caused by a temperature gradient in a pixel portion due to a heat generated from a source signal line driver circuit are suppressed. In a display device including a gate signal line provided in a row direction, a source signal line provided in a column direction, and a light emitting element in a pixel portion arranged in matrix corresponding to the gate signal line and the source signal line, a column of monitor elements is provided beside the pixel portion, a constant current is supplied to each row of the monitor elements, and a voltage generated at the monitor element for each row of pixels is applied to light emitting elements of the corresponding row.
摘要翻译：显示装置抑制由温度变化引起的提供给发光元件的电流值的变化的影响。特别地，抑制了由源极信号线驱动电路产生的热量引起的象素部分温度梯度引起的亮度变化。在包括沿行方向设置的栅极信号线，沿列方向设置的源极信号线和与栅极信号线和源极信号线对应地排列成矩阵的像素部中的发光元件的显示装置中，监视器元件列设置在像素部分的旁边，向监视器元件的每一行提供恒定电流，并且将针对每行像素的监视元件产生的电压施加到相应行的发光元件。

10. 发明申请

US20120287359A1 DISPLAY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：显示装置及其制造方法
公开(公告)号：US20120287359A1
公开(公告)日：2012-11-15
申请号：US13461809
申请日：2012-05-02
申请人： Shunpei YAMAZAKI , Jun KOYAMA
发明人： Shunpei YAMAZAKI , Jun KOYAMA
IPC分类号： G02F1/1343
CPC分类号： G02F1/1347 , G02B27/2214 , G02B27/2264 , H04N13/31 , H04N13/315
摘要： A display device includes a display panel and a shutter panel provided on a viewable side of the display panel. The shutter panel includes a plurality of first transparent electrodes provided over a first substrate, a plurality of second transparent electrodes provided over a second substrate, and a liquid crystal provided between the first substrate and the second substrate. The first transparent electrodes and the second transparent electrodes are arranged in striped patterns in a first direction and are both spaced in a second direction intersecting the first direction. Potentials of the first transparent electrodes and potentials of the second transparent electrodes are controlled to adjust an alignment of the liquid crystal, so that the shutter panel is provided with light-shielding regions arranged in a striped pattern in the first direction and spaced in the second direction and light-transmitting regions each of which is provided between the light-shielding regions.
摘要翻译：显示装置包括显示面板和设置在显示面板的可视侧的快门面板。快门面板包括设置在第一基板上的多个第一透明电极，设置在第二基板上的多个第二透明电极以及设置在第一基板和第二基板之间的液晶。第一透明电极和第二透明电极在第一方向上以条纹图案布置，并且在与第一方向相交的第二方向上都间隔开。控制第一透明电极的电位和第二透明电极的电位以调节液晶的对准，使得快门面板设置有在第一方向上以条纹图案排列的光屏蔽区域，并且在第二透明电极方向和透光区域设置在遮光区域之间。

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