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1. 发明申请

US20080203388A1 Apparatus and method for detection of edge damages 审中-公开
标题翻译：用于检测边缘损伤的装置和方法
公开(公告)号：US20080203388A1
公开(公告)日：2008-08-28
申请号：US11712355
申请日：2007-02-28
申请人： Jun He , Jeff Hicks , Chris Litteken , Tom Marieb , Alan Lucero , Jose Maiz , Jun He , Jeffrey Morisson Hicks
发明人： Jun He , Jeff Hicks , Chris Litteken , Tom Marieb , Alan Lucero , Jose Maiz , Jun He , Jeffrey Morisson Hicks
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/32 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one or more conductive paths intersecting a plurality of metallization layers in the semiconductor device. A relative change in an electrical characteristic of the continuity structure(s) is monitored to ascertain whether or not an edge damage is present.
摘要翻译：本发明的实施例能够检测半导体器件中的边缘损伤。为此，可以提供一个或多个连续性结构，其中每个结构包括布置在半导体器件的有源电路和金属化层的周边之间的起伏布置。连续性结构形成与半导体器件中的多个金属化层交叉的一个或多个导电路径。监视连续性结构的电特性的相对变化，以确定是否存在边缘损伤。

2. 外观设计

USD965692S1 Spinner toy 有权
公开(公告)号：USD965692S1
公开(公告)日：2022-10-04
申请号：US29819424
申请日：2021-12-15
申请人： Jun He
设计人： Jun He

3. 发明授权

US08704336B2 Selective removal of on-die redistribution interconnects from scribe-lines 有权
标题翻译：从划线中选择性地去除片上再分配互连
公开(公告)号：US08704336B2
公开(公告)日：2014-04-22
申请号：US11848879
申请日：2007-08-31
申请人： Jun He , Kevin J. Lee , Subhash Joshi
发明人： Jun He , Kevin J. Lee , Subhash Joshi
IPC分类号： H01L23/544
CPC分类号： H01L22/32 , H01L2924/0002 , H01L2924/00
摘要： Selective removal of on-die redistribution interconnect material from a scribe-line region is generally described. In one example, an apparatus includes a first semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, a second semiconductor die coupled with the first semiconductor die, the second semiconductor die having a redistribution layer comprising redistribution dielectric and one or more redistribution metal interconnects, and a scribe-line region disposed between the first semiconductor die and second semiconductor die, the scribe-line region having a majority or substantially all of redistribution dielectric or redistribution metal, or suitable combinations thereof, selectively removed to enable die singulation through the scribe-line region.
摘要翻译：通常描述从划线区域选择性地去除片上再分布互连材料。在一个示例中，一种装置包括具有再分布层的第一半导体管芯，其包括再分布电介质和一个或多个再分布金属互连，与第一半导体管芯耦合的第二半导体管芯，第二半导体管芯具有包括再分布电介质的再分配层和一个或更多的再分配金属互连，以及设置在第一半导体管芯和第二半导体管芯之间的划线区域，划分线区域具有大部分或基本上全部的再分布电介质或再分配金属或其合适的组合，通过划线区划分。

4. 发明授权

US08435410B2 Surfactant-based monolithic columns, methods for making the same, and method for using the same 有权
标题翻译：基于表面活性剂的整体柱，其制备方法及其使用方法
公开(公告)号：US08435410B2
公开(公告)日：2013-05-07
申请号：US12922357
申请日：2009-03-30
申请人： Shahab Ahmed Shamsi , Congying Gu , Jun He
发明人： Shahab Ahmed Shamsi , Congying Gu , Jun He
IPC分类号： B01D15/08
CPC分类号： C08J9/127 , B01J20/261 , B01J20/267 , B01J20/28042 , B01J20/285 , B01J2220/82 , G01N2030/528
摘要： A method for making a surfactant-based monolithic column is provided. The method comprises providing a mixture comprising at least one surfactant monomer, at least one crosslinker, at least one initiator, and at least one porogen and polymerizing the mixture to form the surfactant-based monolithic column. The present disclosure also provides a surfactant-based monolithic column, a method for separating molecules, and a process for preparing a surfactant monomer.
摘要翻译：提供了制备基于表面活性剂的整体柱的方法。该方法包括提供包含至少一种表面活性剂单体，至少一种交联剂，至少一种引发剂和至少一种致孔剂的混合物，并使混合物聚合以形成基于表面活性剂的整体柱。本公开还提供了一种基于表面活性剂的整体柱，分离分子的方法和制备表面活性剂单体的方法。

5. 发明授权

US08368171B2 Methods of forming electromigration and thermal gradient based fuse structures 有权
标题翻译：形成电迁移和基于热梯度的熔丝结构的方法
公开(公告)号：US08368171B2
公开(公告)日：2013-02-05
申请号：US11605119
申请日：2006-11-27
申请人： Jose A. Maiz , Jun He , Mark Bohr
发明人： Jose A. Maiz , Jun He , Mark Bohr
IPC分类号： H01L23/52 , H01L29/40
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括通过在第一互连结构上形成至少一个通孔来形成金属熔丝结构，将所述至少一个通孔与阻挡层衬里，然后在所述至少一个通孔上形成第二互连结构。

6. 发明申请

US20120007242A1 INTERCONNECTS HAVING SEALING STRUCTURES TO ENABLE SELECTIVE METAL CAPPING LAYERS 审中-公开
标题翻译：具有密封结构的互连使得选择性金属填充层
公开(公告)号：US20120007242A1
公开(公告)日：2012-01-12
申请号：US13242988
申请日：2011-09-23
申请人： Jun He , Kevin J. Fischer , Ying Zhou , Peter K. Moon
发明人： Jun He , Kevin J. Fischer , Ying Zhou , Peter K. Moon
IPC分类号： H01L23/48
CPC分类号： H01L21/76849 , H01L21/0217 , H01L21/02252 , H01L21/32053 , H01L21/76802 , H01L21/76834 , H01L21/76844 , H01L21/76856 , H01L21/76865 , H01L21/76877 , H01L21/76888 , H01L23/5283 , H01L23/53209 , H01L23/53228 , H01L23/53238 , H01L23/53266 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
摘要翻译：制造用于微电子器件的封盖互连的方法，其包括封盖层和互连件之间的任何间隙的密封特征以及由其形成的结构。密封特征改善了互连的封装，其基本上减少或防止导电材料从封盖互连件的电迁移和/或扩散。

7. 发明申请

US20110138396A1 METHOD AND SYSTEM FOR DATA DISTRIBUTION IN HIGH PERFORMANCE COMPUTING CLUSTER 失效
标题翻译：高性能计算集群数据分配方法与系统
公开(公告)号：US20110138396A1
公开(公告)日：2011-06-09
申请号：US12955280
申请日：2010-11-29
申请人： Qi Chen , Jun He , Guang Lei Li , Huo Ding Li , Wei Liu
发明人： Qi Chen , Jun He , Guang Lei Li , Huo Ding Li , Wei Liu
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： The present invention discloses a method and system for data distribution in a High-Performance Computing cluster, the High-Performance Computing cluster comprising a Management node and M computation nodes where M is an integer greater than or equal to 2, the Management node distributing the specified data to the M computation nodes, the method comprising steps of: dividing the M computation nodes into m layers where m is an integer greater than or equal to 2; dividing the specified data into k shares where k is an integer greater than or equal to 2; distributing, by the Management node, the k shares of data to a first layer of computation nodes as sub-nodes thereof, each of the first layer of computation nodes obtaining at least one share of data therein; distributing, by each of the computation nodes, the at least one share of data distributed by a parent node thereof to sub-computation nodes thereof; and requesting, by each of the computation nodes, the remaining specified data to other computation nodes, to thereby obtain all the specified data. The method and system enable data to be distributed rapidly to various computation nodes in the High-Performance Computing cluster.
摘要翻译：本发明公开了一种高性能计算集群中数据分发的方法和系统，该高性能计算集群包括管理节点和M个计算节点，其中M为大于或等于2的整数，管理节点分发指定的数据到M个计算节点，该方法包括以下步骤：将M个计算节点划分为m个层，其中m是大于或等于2的整数; 将指定的数据划分为k个共享，其中k是大于或等于2的整数; 由管理节点将k份数据分配给第一层计算节点作为其子节点，第一层计算节点中的每一个在其中获得至少一份数据; 由每个计算节点将由其父节点分发的数据的至少一个共享分配给其子计算节点; 并且通过每个计算节点向其他计算节点请求剩余的指定数据，从而获得所有指定的数据。该方法和系统将数据快速分发到高性能计算集群中的各种计算节点。

8. 发明申请

US20070238309A1 Method of reducing interconnect line to line capacitance by using a low k spacer 审中-公开
标题翻译：通过使用低k间隔来减少互连线对线电容的方法
公开(公告)号：US20070238309A1
公开(公告)日：2007-10-11
申请号：US11394913
申请日：2006-03-31
申请人： Jun He , Kevin Fischer
发明人： Jun He , Kevin Fischer
IPC分类号： H01L21/31 , H01L21/469
CPC分类号： H01L21/76843 , H01L21/76832 , H01L21/76849
摘要： A method is described of reducing the line to line capacitance within semiconductor devices and a device demonstrating the same. The device includes a spacer layer disposed between an etch stop material and a conductive layer. Separating the etch stop layer from the conductive layers by the spacer layer may decrease the line to line capacitance significantly in a semiconductor device.
摘要翻译：描述了一种降低半导体器件内的线间电容的方法和展示其的器件。该器件包括设置在蚀刻停止材料和导电层之间的间隔层。通过间隔层将蚀刻停止层与导电层分离可以在半导体器件中显着地减小线对电容。

9. 发明授权

US07175970B2 Mechanically robust interconnect for low-k dielectric material using post treatment 有权
标题翻译：使用后处理的低k电介质材料的机械稳健互连
公开(公告)号：US07175970B2
公开(公告)日：2007-02-13
申请号：US11286783
申请日：2005-11-22
申请人： Jun He , Jihperng Leu
发明人： Jun He , Jihperng Leu
IPC分类号： G03C5/00 , H01L21/31
CPC分类号： H01L21/76831 , H01L21/76801 , H01L21/76808 , H01L21/7682 , H01L21/76825 , H01L23/5222 , H01L23/5226 , H01L2924/0002 , Y10S430/143 , H01L2924/00
摘要： In an embodiment, a trench is formed above a via from a photo resist (PR) trench pattern in a dielectric layer. The trench is defined by two sidewall portions and base portions. The base portions of the sidewalls are locally treated by a post treatment using the PR trench pattern as mask to enhance mechanical strength of portions of the dielectric layer underneath the base portions. Seed and barrier layers are deposited on the trench and the via. The trench and via are filled with a metal layer. In another embodiment, a trench is formed from a PR trench pattern in a dielectric layer. A pillar PR is deposited and etched to define a pillar opening having a pillar surface. The pillar opening is locally treated on the pillar surface by a post treatment to enhance mechanical strength of portion of the dielectric layer underneath the pillar surface.
摘要翻译：在一个实施例中，在电介质层中的光致抗蚀剂（PR）沟槽图案的通孔上方形成沟槽。沟槽由两个侧壁部分和基部限定。通过使用PR沟槽图案作为掩模的后处理对侧壁的基部进行局部处理，以增强在基部下方的介电层的部分的机械强度。种子和阻挡层沉积在沟槽和通孔上。沟槽和通孔填充有金属层。在另一个实施例中，沟槽由电介质层中的PR沟槽图案形成。沉积并蚀刻柱PR以限定具有柱表面的柱开口。通过后处理在柱面上局部处理立柱开口，以提高柱表面下方的电介质层的部分的机械强度。

10. 发明申请

US20060261437A1 Methods of forming electromigration and thermal gradient based fuse structures 有权
公开(公告)号：US20060261437A1
公开(公告)日：2006-11-23
申请号：US11133835
申请日：2005-05-20
申请人： Jose Maiz , Jun He , Mark Bohr
发明人： Jose Maiz , Jun He , Mark Bohr
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

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