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1. 发明申请

US20060043579A1 Transistor performance enhancement using engineered strains 失效
标题翻译：使用工程菌株的晶体管性能提升
公开(公告)号：US20060043579A1
公开(公告)日：2006-03-02
申请号：US10930247
申请日：2004-08-31
申请人： Jun He , Zhiyong Ma , Jose Maiz , Mark Bohr , Martin Giles , Guanghai Xu
发明人： Jun He , Zhiyong Ma , Jose Maiz , Mark Bohr , Martin Giles , Guanghai Xu
IPC分类号： H01L23/34
CPC分类号： H01L29/7842 , H01L21/823807 , H01L23/42 , H01L2224/16 , H01L2224/73253 , H01L2924/00011 , H01L2924/00014 , H01L2924/01019 , H01L2924/01087 , H01L2924/01322 , H01L2924/10253 , H01L2924/15311 , H01L2924/16152 , H01L2924/00 , H01L2224/0401
摘要： A semiconductor substrate having metal oxide semiconductor (MOS) devices, such as an integrated circuit die, is mechanically coupled to a stress structure to apply a stress that improves the performance of at least a portion of the MOS devices on the die.
摘要翻译：具有诸如集成电路管芯的金属氧化物半导体（MOS）器件的半导体衬底被机械耦合到应力结构，以施加提高模具上的至少一部分MOS器件的性能的应力。

2. 发明申请

US20060261437A1 Methods of forming electromigration and thermal gradient based fuse structures 有权
公开(公告)号：US20060261437A1
公开(公告)日：2006-11-23
申请号：US11133835
申请日：2005-05-20
申请人： Jose Maiz , Jun He , Mark Bohr
发明人： Jose Maiz , Jun He , Mark Bohr
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.

3. 发明申请

US20070069331A1 Methods of forming electromigration and thermal gradient based fuse structures 有权
标题翻译：形成电迁移和基于热梯度的熔丝结构的方法
公开(公告)号：US20070069331A1
公开(公告)日：2007-03-29
申请号：US11605119
申请日：2006-11-27
申请人： Jose Maiz , Jun He , Mark Bohr
发明人： Jose Maiz , Jun He , Mark Bohr
IPC分类号： H01L29/00
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括通过在第一互连结构上形成至少一个通孔来形成金属熔丝结构，将所述至少一个通孔与阻挡层衬里，然后在所述至少一个通孔上形成第二互连结构。

4. 发明申请

US20080203388A1 Apparatus and method for detection of edge damages 审中-公开
标题翻译：用于检测边缘损伤的装置和方法
公开(公告)号：US20080203388A1
公开(公告)日：2008-08-28
申请号：US11712355
申请日：2007-02-28
申请人： Jun He , Jeff Hicks , Chris Litteken , Tom Marieb , Alan Lucero , Jose Maiz , Jun He , Jeffrey Morisson Hicks
发明人： Jun He , Jeff Hicks , Chris Litteken , Tom Marieb , Alan Lucero , Jose Maiz , Jun He , Jeffrey Morisson Hicks
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L22/32 , H01L23/585 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention enable detection of edge damages in semiconductor devices. To this purpose, one or more continuity structures may be provided, where each structure comprises an undulating arrangement disposed between active circuits of the semiconductor device and a perimeter of the metallization layers. The continuity structure(s) forms one or more conductive paths intersecting a plurality of metallization layers in the semiconductor device. A relative change in an electrical characteristic of the continuity structure(s) is monitored to ascertain whether or not an edge damage is present.
摘要翻译：本发明的实施例能够检测半导体器件中的边缘损伤。为此，可以提供一个或多个连续性结构，其中每个结构包括布置在半导体器件的有源电路和金属化层的周边之间的起伏布置。连续性结构形成与半导体器件中的多个金属化层交叉的一个或多个导电路径。监视连续性结构的电特性的相对变化，以确定是否存在边缘损伤。

5. 发明授权

US06919637B2 Interconnect structure for an integrated circuit and method of fabrication 失效
标题翻译：集成电路的互连结构和制造方法
公开(公告)号：US06919637B2
公开(公告)日：2005-07-19
申请号：US10261543
申请日：2002-09-30
申请人： Jun He , Jose Maiz , Hyun-Mog Park
发明人： Jun He , Jose Maiz , Hyun-Mog Park
IPC分类号： H01L23/522 , H01L23/532 , H01L29/40
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.
摘要翻译：公开了一种具有多级导体的集成电路的互连结构。在不具有通孔的位置处，在相邻层中的导体之间形成用于机械支撑的介电柱。支柱对于低k ILD或空气电介质特别有用。

6. 发明申请

US20050221604A1 Interconnect structure for an integrated circuit and method of fabrication 有权
公开(公告)号：US20050221604A1
公开(公告)日：2005-10-06
申请号：US11142437
申请日：2005-05-31
申请人： Jun He , Jose Maiz , Hyun-Mog Park
发明人： Jun He , Jose Maiz , Hyun-Mog Park
IPC分类号： H01L23/522 , H01L23/532 , H01L21/4763
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.

7. 发明授权

US07151051B2 Interconnect structure for an integrated circuit and method of fabrication 有权
标题翻译：集成电路的互连结构和制造方法
公开(公告)号：US07151051B2
公开(公告)日：2006-12-19
申请号：US11142437
申请日：2005-05-31
申请人： Jun He , Jose Maiz , Hyun-Mog Park
发明人： Jun He , Jose Maiz , Hyun-Mog Park
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： An interconnect structure for an integrated circuit having several levels of conductors is disclosed. Dielectric pillars for mechanical support are formed between conductors in adjacent layers at locations that do not have vias. The pillars are particularly useful with low-k ILD or air dielectric.
摘要翻译：公开了一种具有多级导体的集成电路的互连结构。在不具有通孔的位置处，在相邻层中的导体之间形成用于机械支撑的介电柱。支柱对于低k ILD或空气电介质特别有用。

8. 发明授权

US07889013B2 Microelectronic die having CMOS ring oscillator thereon and method of using same 有权
标题翻译：具有CMOS环形振荡器的微电子管芯及其使用方法
公开(公告)号：US07889013B2
公开(公告)日：2011-02-15
申请号：US11846190
申请日：2007-08-28
申请人： Gerald S. Leatherman , Jun He , Jose Maiz
发明人： Gerald S. Leatherman , Jun He , Jose Maiz
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , G01R31/2884 , H01L22/34
摘要： A microelectronic die including a CMOS ring oscillator thereon, and a method of using the same. The microelectronic die includes: a die substrate; and a plurality of CMOS ring oscillators on the die substrate, the ring oscillators being disposed at regions of the die substrate that are adapted to exhibit differing strain responses to package-included stress with respect to one another. A method of determining mechanical stress on a die which includes providing a die substrate in a CMOS ring oscillator on a die substrate. A frequency counter is coupled to the ring oscillator to measure a frequency of the ring oscillator to generate a frequency data signal therefrom. The frequency data signal is used to determine the mechanical stress on the die at a location of the ring oscillator.
摘要翻译：包括其上的CMOS环形振荡器的微电子管芯及其使用方法。微电子管芯包括：管芯基板; 以及在所述管芯衬底上的多个CMOS环形振荡器，所述环形振荡器设置在所述管芯衬底的适于相对于彼此显示对于包装应力的应力的不同应变响应的区域处。一种确定模具上的机械应力的方法，其包括在芯片基板上的CMOS环形振荡器中提供管芯衬底。频率计数器耦合到环形振荡器以测量环形振荡器的频率以从其产生频率数据信号。频率数据信号用于确定环形振荡器位置处芯片上的机械应力。

9. 发明申请

US20090058540A1 Microelectronic Die Having CMOS Ring Oscillator Thereon And Method of Using Same 有权
标题翻译：具有CMOS环形振荡器的微电子芯片及其使用方法
公开(公告)号：US20090058540A1
公开(公告)日：2009-03-05
申请号：US11846190
申请日：2007-08-28
申请人： Gerald S. Leatherman , Jun He , Jose Maiz
发明人： Gerald S. Leatherman , Jun He , Jose Maiz
IPC分类号： H03K3/03
CPC分类号： H03K3/0315 , G01R31/2884 , H01L22/34
摘要： A microelectronic die including a CMOS ring oscillator thereon, and a method of using the same. The microelectronic die includes: a die substrate; and a plurality of CMOS ring oscillators on the die substrate, the ring oscillators being disposed at regions of the die substrate that are adapted to exhibit differing strain responses to package-induced stress with respect to one another.
摘要翻译：包括其上的CMOS环形振荡器的微电子管芯及其使用方法。微电子管芯包括：管芯基板; 以及在所述管芯衬底上的多个CMOS环形振荡器，所述环形振荡器设置在所述管芯衬底的适于相对于彼此显示对封装引起的应力的不同应变响应的区域处。

10. 发明授权

US08368171B2 Methods of forming electromigration and thermal gradient based fuse structures 有权
标题翻译：形成电迁移和基于热梯度的熔丝结构的方法
公开(公告)号：US08368171B2
公开(公告)日：2013-02-05
申请号：US11605119
申请日：2006-11-27
申请人： Jose A. Maiz , Jun He , Mark Bohr
发明人： Jose A. Maiz , Jun He , Mark Bohr
IPC分类号： H01L23/52 , H01L29/40
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming a microelectronic structure are described. Embodiments of those methods include forming a metallic fuse structure by forming at least one via on a first interconnect structure, lining the at least one via with a barrier layer, and then forming a second interconnect structure on the at least one via.
摘要翻译：描述形成微电子结构的方法。这些方法的实施例包括通过在第一互连结构上形成至少一个通孔来形成金属熔丝结构，将所述至少一个通孔与阻挡层衬里，然后在所述至少一个通孔上形成第二互连结构。

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