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1. 发明授权

US5057462A Compensation of lithographic and etch proximity effects 失效
标题翻译：屈光度和蚀刻近似效应的补偿
公开(公告)号：US5057462A
公开(公告)日：1991-10-15
申请号：US413356
申请日：1989-09-27
申请人： Juli H. Eisenberg , Larry B. Fritzinger , Chong-Cheng Fu , Taeho Kook , Thomas M. Wolf
发明人： Juli H. Eisenberg , Larry B. Fritzinger , Chong-Cheng Fu , Taeho Kook , Thomas M. Wolf
IPC分类号： G03F1/08 , G03F7/20 , H01L21/027 , H01L21/30 , H01L21/302 , H01L21/3065
CPC分类号： G03F7/20 , Y10S438/941 , Y10S438/948
摘要： In the manufacture of integrated-circuit devices, patterned features are made on a substrate by etching a deposited layer. The pattern comprises features which are closely spaced, as well as others which are more isolated. Etching is in approximate conformance with a lithographically defined resist pattern which in turn is in approximate conformance with a desired pattern. A processing parameter such as, e.g., resist layer thickness is chosen such that an etched pattern is obtained which approximates a desired pattern more closely than a lithographically defined resist pattern.

2. 发明授权

US5891784A Transistor fabrication method 失效
标题翻译：晶体管制造方法
公开(公告)号：US5891784A
公开(公告)日：1999-04-06
申请号：US430084
申请日：1995-04-27
申请人： Wan Yee Cheung , Sailesh Chittipeddi , Chong-Cheng Fu , Taeho Kook , Avinoam Kornblit , Steven Alan Lytle , Kurt George Steiner , Tungsheng Yang
发明人： Wan Yee Cheung , Sailesh Chittipeddi , Chong-Cheng Fu , Taeho Kook , Avinoam Kornblit , Steven Alan Lytle , Kurt George Steiner , Tungsheng Yang
IPC分类号： H01L21/027 , H01L21/336 , H01L21/331
CPC分类号： H01L21/0276 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/6659 , Y10S438/952
摘要： A method of forming low stack height transistors having controllable linewidth in an integrated circuit without channeling is disclosed. A disposable hardmask of doped glass is utilized to define the gate and subsequently protect the gate (and the underlying substrate) during ion implantation which forms the source and drains. An anti-reflective coating helps protect against reflective gate notching. A variety of silicided and non-silicided) structures may be formed.
摘要翻译：公开了一种形成集成电路中没有通道的可控线宽的低堆叠高度晶体管的方法。使用掺杂玻璃的一次性硬掩模来限定栅极并且随后在形成源极和漏极的离子注入期间保护栅极（和下面的衬底）。抗反射涂层有助于防止反光门开槽。可以形成各种硅化和非硅化的结构。

3. 发明申请

US20080085609A1 METHOD FOR PROTECTING HIGH-TOPOGRAPHY REGIONS DURING PATTERNING OF LOW-TOPOGRAPHY REGIONS 审中-公开
标题翻译：保护低地层地区高原地区的方法
公开(公告)号：US20080085609A1
公开(公告)日：2008-04-10
申请号：US11461033
申请日：2006-07-31
申请人： James E. Vasek , Nicole R. Ellis , Chong-Cheng Fu
发明人： James E. Vasek , Nicole R. Ellis , Chong-Cheng Fu
IPC分类号： H01L21/31
CPC分类号： H01L21/32139 , H01L27/105 , H01L27/11526 , H01L27/11539
摘要： A method for protecting at least one high-topography region on a substrate having both the at least one high-topography region and the at least one low-topography region is provided. The method comprises patterning a thick photo-resist layer having a first thickness, such that the thick photo-resist layer is formed on at least a portion of only the at least one high-topography region, wherein the high-topography region comprises a plurality of semiconductor devices of a first type. The method further comprises patterning a thin photo-resist layer having a second thickness, wherein the first thickness is greater than the second thickness, such that the patterned thin photo-resist layer is formed on at least a portion of only the at least one low-topography region. The method further comprises forming a plurality of semiconductor devices of a second type in the at least the portion of the low-topography region. The method further comprises removing both the thick photo-resist layer and the thin photo-resist layer.
摘要翻译：提供了一种用于保护具有至少一个高地形区域和至少一个低地形区域的基底上的至少一个高地形区域的方法。该方法包括图案化具有第一厚度的厚的光致抗蚀剂层，使得厚的光致抗蚀剂层形成在仅至少一个高地形区域的至少一部分上，其中高地形区域包括多个的第一类半导体器件。该方法还包括对具有第二厚度的薄的光致抗蚀剂层进行图案化，其中第一厚度大于第二厚度，使得图案化的光致抗蚀剂层形成在至少一个低至少一个的至少一部分上地形区域。该方法还包括在低地形区域的至少一部分中形成第二类型的多个半导体器件。该方法还包括去除厚的光致抗蚀剂层和薄的光致抗蚀剂层。

4. 发明申请

US20120007155A1 SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS 审中-公开
标题翻译：具有扩展活动区域的半导体器件
公开(公告)号：US20120007155A1
公开(公告)日：2012-01-12
申请号：US13235580
申请日：2011-09-19
申请人： MARK D. HALL , Glenn C. Abeln , Chong-Cheng Fu
发明人： MARK D. HALL , Glenn C. Abeln , Chong-Cheng Fu
IPC分类号： H01L29/772
CPC分类号： H01L21/76232 , H01L21/8252 , H01L21/84 , H01L27/0207 , H01L27/11
摘要： A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.
摘要翻译：在半导体层中和半导体层上实现制造半导体器件的方法。在第一有效区域附近形成沟槽。沟槽填充绝缘材料。掩模特征形成在沟槽的中心部分上，以在掩蔽特征的第一侧和第一有效区域之间露出沟槽的第一侧。蚀刻到沟槽的第一侧的步骤在沟槽中留下第一凹槽。在第一凹槽中生长第一外延区域以使第一有源区域延伸以包括第一凹部，从而形成延伸的第一有源区域。

5. 发明授权

US08062953B2 Semiconductor devices with extended active regions 有权
标题翻译：半导体器件具有扩展的有源区
公开(公告)号：US08062953B2
公开(公告)日：2011-11-22
申请号：US12182421
申请日：2008-07-30
申请人： Mark D. Hall , Glenn C. Abeln , Chong-Cheng Fu
发明人： Mark D. Hall , Glenn C. Abeln , Chong-Cheng Fu
IPC分类号： H01L21/76
CPC分类号： H01L21/76232 , H01L21/8252 , H01L21/84 , H01L27/0207 , H01L27/11
摘要： A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.
摘要翻译：在半导体层中和半导体层上实现制造半导体器件的方法。在第一有效区域附近形成沟槽。沟槽填充绝缘材料。掩模特征形成在沟槽的中心部分上，以在掩蔽特征的第一侧和第一有效区域之间露出沟槽的第一侧。蚀刻到沟槽的第一侧的步骤在沟槽中留下第一凹槽。在第一凹槽中生长第一外延区域以使第一有源区域延伸以包括第一凹部，从而形成延伸的第一有源区域。

6. 发明授权

US4431936A Transducer structure for generating uniform and focused ultrasonic beams and applications thereof 失效
标题翻译：用于产生均匀和聚焦的超声波束的传感器结构及其应用
公开(公告)号：US4431936A
公开(公告)日：1984-02-14
申请号：US350020
申请日：1982-02-18
申请人： Chong-Cheng Fu , Levy Gerzberg
发明人： Chong-Cheng Fu , Levy Gerzberg
IPC分类号： A61B5/026 , G01F1/66 , G01P5/24 , G10K11/26 , G10K11/34 , H01L41/04
CPC分类号： G01F1/662 , G01P5/24 , G10K11/26 , G10K11/348 , G01N2291/02836
摘要： Transducer structures for use in volume flow measurements which generate a first uniform beam and a second focused beam within the uniform beam. The transducer may include concentric elements, a linear array, or combinations thereof. In a two element concentric array, a central disc generates a uniform beam and a peripheral annular element having a lens thereon defines a second focused beam within the first beam. In a linear array, a plurality of juxtaposed linear elements define a scan surface, and a segmented element within the linear element array defines a focused reference sample volume within the scanned surface. A concentric array having a plurality of annular elements is driven with amplitude weighting of each element, in accordance with a Fourier-Bessel approximation to the desired beam pattern, thereby electronically achieving ultrasonic beam width control.

7. 发明申请

US20110089581A1 SEMICONDUCTOR WAFER HAVING SCRIBE LANE ALIGNMENT MARKS FOR REDUCING CRACK PROPAGATION 有权
标题翻译：具有用于减少裂纹扩展的可选择的对准标记的半导体波形
公开(公告)号：US20110089581A1
公开(公告)日：2011-04-21
申请号：US12581549
申请日：2009-10-19
申请人： Victor Pol , Chong-Cheng Fu
发明人： Victor Pol , Chong-Cheng Fu
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/5446 , H01L2924/0002 , H01L2924/00
摘要： A wafer including at least a first die and at least a second die, wherein the first die and the second die are separated from each other by an area located between the first die and the second die, is provided. The wafer further includes an alignment mark group used for aligning the wafer to a tool used for patterning the wafer. The alignment mark group is located entirely within the area between the first die and the second die and the alignment mark group includes a plurality of alignment lines, and wherein each line of the plurality of alignment lines is formed using a plurality of segments separated from each other by a plurality of gaps filled with an insulating material.
摘要翻译：提供包括至少第一管芯和至少第二管芯的晶片，其中所述第一管芯和所述第二管芯彼此分开位于所述第一管芯和所述第二管芯之间的区域。晶片还包括用于将晶片对准用于图案化晶片的工具的对准标记组。对准标记组完全位于第一管芯和第二管芯之间的区域内，并且对准标记组包括多个对准线，并且其中多个对准线中的每条线使用与每个对准线分离的多个段形成另外由填充绝缘材料的多个间隙。

8. 发明申请

US20100025805A1 SEMICONDUCTOR DEVICES WITH EXTENDED ACTIVE REGIONS 有权
标题翻译：具有扩展活动区域的半导体器件
公开(公告)号：US20100025805A1
公开(公告)日：2010-02-04
申请号：US12182421
申请日：2008-07-30
申请人： MARK D. HALL , Glenn C. Abeln , Chong-Cheng Fu
发明人： MARK D. HALL , Glenn C. Abeln , Chong-Cheng Fu
IPC分类号： H01L21/762 , H01L27/02
CPC分类号： H01L21/76232 , H01L21/8252 , H01L21/84 , H01L27/0207 , H01L27/11
摘要： A method of making a semiconductor device is achieved in and over a semiconductor layer. A trench is formed adjacent to a first active area. The trench is filled with insulating material. A masking feature is formed over a center portion of the trench to expose a first side of the trench between a first side of the masking feature and the first active area. A step of etching into the first side of the trench leaves a first recess in the trench. A first epitaxial region is grown in the first recess to extend the first active area to include the first recess and thereby form an extended first active region.
摘要翻译：在半导体层中和半导体层上实现制造半导体器件的方法。在第一有效区域附近形成沟槽。沟槽填充绝缘材料。掩模特征形成在沟槽的中心部分上，以在掩蔽特征的第一侧和第一有效区域之间露出沟槽的第一侧。蚀刻到沟槽的第一侧的步骤在沟槽中留下第一凹槽。在第一凹槽中生长第一外延区域以使第一有源区域延伸以包括第一凹部，从而形成延伸的第一有源区域。

9. 发明申请

US20070048985A1 Dual silicide semiconductor fabrication process 有权
标题翻译：双硅化物半导体制造工艺
公开(公告)号：US20070048985A1
公开(公告)日：2007-03-01
申请号：US11213470
申请日：2005-08-26
申请人： Dharmesh Jawarani , Chong-Cheng Fu , Mark Hall
发明人： Dharmesh Jawarani , Chong-Cheng Fu , Mark Hall
IPC分类号： H01L21/28
CPC分类号： H01L29/66507
摘要： A semiconductor fabrication process includes forming a gate stack overlying semiconductor substrate. Source/drain regions are formed in the substrate laterally aligned to the gate stack. A hard mask is formed overlying a gate electrode of the gate stack. A first silicide is then formed selectively over the source/drain regions. After removing the hard mask, a second silicide is selectively formed on the gate electrode. The first silicide and the second silicide are different. Forming the gate stack may include forming a gate dielectric on the semiconductor substrate and a polysilicon gate electrode on the gate dielectric. The gate electrode may have a line width of less than 40 nm. Forming the second silicide may include forming nickel silicide in upper portions of the gate electrode.
摘要翻译：半导体制造工艺包括形成覆盖半导体衬底的栅叠层。源极/漏极区域形成在与栅极叠层横向对准的衬底中。形成覆盖栅极堆叠的栅电极的硬掩模。然后在源极/漏极区域上选择性地形成第一硅化物。在去除硬掩模之后，在栅电极上选择性地形成第二硅化物。第一硅化物和第二硅化物不同。形成栅极堆叠可以包括在半导体衬底上形成栅极电介质和在栅极电介质上形成多晶硅栅电极。栅电极的线宽可以小于40nm。形成第二硅化物可以包括在栅电极的上部形成硅化镍。

10. 发明授权

US5849440A Process for producing and inspecting a lithographic reticle and fabricating semiconductor devices using same 失效
标题翻译：用于制造和检查光刻掩模版并使用其制造半导体器件的方法
公开(公告)号：US5849440A
公开(公告)日：1998-12-15
申请号：US792670
申请日：1997-01-29
申请人： Kevin D. Lucas , Michael E. Kling , Alfred J. Reich , Chong-Cheng Fu , James Morrow
发明人： Kevin D. Lucas , Michael E. Kling , Alfred J. Reich , Chong-Cheng Fu , James Morrow
IPC分类号： G03F1/00 , G03F1/84 , G03F7/20 , H01L21/027 , G03F9/00
CPC分类号： G03F7/705 , G03F1/84 , G03F7/70433 , G03F7/70633
摘要： A process for fabricating a semiconductor device includes the formation of a lithographic reticle (20) having a lithographic pattern (18) overlying a reticle substrate (10). In one embodiment, a reticle inspection database incorporates altered resolution assisting features (30,32) to inspect the lithographic pattern (18). The dimensional difference between the reticle inspection database and the lithographic reticle is substantially equal to the process bias realized during reticle fabrication. Inspection of the lithographic reticle (20) using a reticle inspection database containing altered resolution assisting features reduces the false detection of defects and provides increased sensitivity in the reticle inspection process.
摘要翻译：一种用于制造半导体器件的工艺包括形成具有覆盖在掩模版衬底（10）上的平版印刷图案（18）的光刻掩模版（20）。在一个实施例中，掩模版检查数据库包含改变的分辨率辅助特征（30,32）以检查光刻图案（18）。标线检查数据库和光刻掩模版之间的尺寸差异基本上等于在掩模版制造期间实现的工艺偏差。使用包含改变的分辨率辅助特征的掩模版检查数据库对光刻掩模版（20）的检查减少了缺陷的错误检测并且在掩模版检查过程中提供了增加的灵敏度。

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