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1. 发明授权

US06621358B2 Differential voltage controlled oscillator, and method therefor 失效
标题翻译：差分压控振荡器及其方法
公开(公告)号：US06621358B2
公开(公告)日：2003-09-16
申请号：US10015384
申请日：2001-12-17
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Ivan Vo
IPC分类号： H03B500
CPC分类号： H03K5/133 , H03K3/0322 , H03K2005/00208 , H03K2005/00234
摘要： In a first form, a voltage controlled oscillator includes delay cells connected in a ring, and control elements connected to selectively bypass respective sets of the delay cells. The delay cells are operable to receive respective differential inputs and to generate inverted outputs. The control elements are operable to receive respective differential inputs and to generate non-inverted outputs with variable delays. The control element delays are variable responsive to respective differential control voltages.
摘要翻译：在第一形式中，压控振荡器包括以环形连接的延迟单元，以及连接到选择性地旁路各组延迟单元的控制元件。延迟单元可操作以接收相应的差分输入并产生反相输出。控制元件可操作以接收相应的差分输入并产生具有可变延迟的非反相输出。响应于各个差分控制电压，控制元件延迟是可变的。

2. 发明授权

US06724221B2 Circuitry having exclusive-OR and latch function, and method therefor 失效
标题翻译：具有异或和锁存功能的电路及其方法
公开(公告)号：US06724221B2
公开(公告)日：2004-04-20
申请号：US10112513
申请日：2002-03-28
申请人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Kevin John Nowka , Li Shi
发明人： Juan-Antonio Carballo , David William Boerstler , Jeffrey L. Burns , Kevin John Nowka , Li Shi
IPC分类号： H03K1921
CPC分类号： H03K19/215
摘要： In one form of the invention, circuitry having exclusive-OR and latch functionality includes timing circuitry and logic circuitry. The circuitry includes a memory, with first and second memory nodes, for storing a state and its complement, and first and second timing circuitry portions, each operable to receive at least one timing signal, coupled to the respective memory nodes. The logic circuitry includes first and second logic circuitry portions, each of which is operable to receive at least first and second data signals. Each of the logic circuitry portions is coupled in series with a conditionally conductive path of one of the respective first and second timing circuitry portions.
摘要翻译：在本发明的一种形式中，具有异或和锁存功能的电路包括定时电路和逻辑电路。电路包括具有用于存储状态及其补码的第一和第二存储器节点的存储器，以及第一和第二定时电路部分，每个定时电路部分可操作以接收耦合到相应存储器节点的至少一个定时信号。逻辑电路包括第一和第二逻辑电路部分，每个逻辑电路部分可操作以接收至少第一和第二数据信号。每个逻辑电路部分与相应的第一和第二定时电路部分之一的条件导电路径串联耦合。

3. 发明授权

US06529084B1 Interleaved feedforward VCO and PLL 有权
标题翻译：交错前馈VCO和PLL
公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译：公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。传统的PLL设计被修改为将误差信号分成AC和DC分量。接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。

4. 发明授权

US06573758B2 Fast, symmetrical XOR/XNOR gate 有权
标题翻译：快速对称XOR / XNOR门
公开(公告)号：US06573758B2
公开(公告)日：2003-06-03
申请号：US09965006
申请日：2001-09-27
申请人： David William Boerstler , Juan Antonio Carballo , Robert Kevin Montoye
发明人： David William Boerstler , Juan Antonio Carballo , Robert Kevin Montoye
IPC分类号： H03K19094
CPC分类号： H03K19/215
摘要： In one aspect, circuitry for a digital logic function includes a first pair of input nodes for receiving respective first and second input signals, a second pair of input nodes for receiving respective complements of the first and second input signals, and an output node. The circuitry has a plurality of PFET-NFET pass gates. Such a pass gate has a first conducting electrode of the pass gate PFET connected to a first conducting electrode of the pass gate NFET, providing a first conducting node of the pass gate, and a second conducting electrode of the pass gate PFET connected to a second conducting electrode of the pass gate NFET, providing a second conducting node of the pass gate. The input nodes are connected to first conducting nodes of respective ones of the plurality of pass gates, and the second conducting nodes of the plurality of pass gates are connected to the circuitry output node.
摘要翻译：在一个方面，用于数字逻辑功能的电路包括用于接收相应的第一和第二输入信号的第一对输入节点，用于接收第一和第二输入信号的相应补码的第二对输入节点和输出节点。该电路具有多个PFET-NFET通孔。这样的栅极具有连接到栅极NFET的第一导电电极的栅极PFET的第一导电电极，提供栅极的第一导电节点，以及连接到第二栅极PFET的栅极PFET的第二导电电极传导门NFET的导电电极，提供通孔的第二导电节点。所述输入节点连接到所述多个通过门中的相应传导门的第一导电节点，并且所述多个通路中的所述第二导通节点连接到所述电路输出节点。

5. 发明申请

US20090326862A1 Clock Duty Cycle Measurement with Charge Pump Without Using Reference Clock Calibration 失效
标题翻译：使用电荷泵进行时钟占空比测量，不使用参考时钟校准
公开(公告)号：US20090326862A1
公开(公告)日：2009-12-31
申请号：US12163081
申请日：2008-06-27
申请人： Jieming Qi , Eskinder Hailu , David William Boerstler , Masaaki Kaneko
发明人： Jieming Qi , Eskinder Hailu , David William Boerstler , Masaaki Kaneko
IPC分类号： G04F1/00 , H03L7/06
CPC分类号： H03K5/1565
摘要： Embodiments of the disclosure provide systems and methods for clock duty cycle measurement. A clock signal and a complement of the clock signal are provided to a charge pump during first and second predetermined timing windows. A charge pump is operable to generate first and second output voltages in response to the clock signal and the complement of the clock signal during the first and second timing windows, respectively. In addition a predetermined positive voltage and a ground voltage are applied to the charge pump during predetermined third and fourth timing windows, respectively. The charge pump is operable to generate third and fourth output voltage signals corresponding to the predetermined positive and ground voltages during the third and fourth timing windows, respectively. The first, second, third and fourth voltages are then used to calculate the duty cycle of the clock.
摘要翻译：本公开的实施例提供了用于时钟占空比测量的系统和方法。时钟信号和时钟信号的补码在第一和第二预定定时窗口期间提供给电荷泵。电荷泵可操作以分别在第一和第二定时窗口期间响应于时钟信号和时钟信号的补码产生第一和第二输出电压。此外，预定的正电压和接地电压分别在预定的第三和第四定时窗口期间施加到电荷泵。电荷泵可操作以分别在第三和第四定时窗口期间产生对应于预定正电压和接地电压的第三和第四输出电压信号。然后，使用第一，第二，第三和第四电压来计算时钟的占空比。

6. 发明授权

US07453293B2 High frequency divider state correction circuit 失效
标题翻译：高分频器状态校正电路
公开(公告)号：US07453293B2
公开(公告)日：2008-11-18
申请号：US11467972
申请日：2006-08-29
申请人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
发明人： David William Boerstler , Eric John Lukes , Hiroki Kihara , James David Strom
IPC分类号： H03K21/00 , H03K23/00 , H03K25/00
CPC分类号： H03K21/406 , G06F7/58
摘要： The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
摘要翻译：本发明提供一种自校正状态电路。第一触发器被配置为接收时钟输入和第一数据输入，并且响应于时钟输入和第一数据输入而产生第一输出。第二触发器耦合到第一触发器并且被配置为接收时钟输入并且接收第一输出作为第二数据输入，并且响应于时钟输入和第一输出而产生第二输出。第一校正电路耦合到第二触发器并且被配置为产生校正输出。第三触发器耦合到第一校正电路并且被配置为接收时钟输入并且接收校正的输出作为第三数据输入，并且响应于时钟输入和第三数据输入而产生第三输出。

7. 发明申请

US20080272820A1 Circuit to Reduce Transient Current Swings During Mode Transitions of High Frequency/High Power Chips 有权
标题翻译：在高频/高功率芯片模式转换期间减少瞬态电流摆幅的电路
公开(公告)号：US20080272820A1
公开(公告)日：2008-11-06
申请号：US12132871
申请日：2008-06-04
申请人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
发明人： David William Boerstler , Eskinder Hailu , Mack Wayne Riley , Michael Fan Wang
IPC分类号： H03K3/00
CPC分类号： H03K23/662 , G06F1/3203 , G06F1/324 , Y02D10/126
摘要： A method, an apparatus, and a computer program are provided to reduce transient current swings during mode transitions. Traditionally, transient supply voltage fluctuations on a chip account for a large portion of the power supply. The number of series inductances and resistances are typically minimized, while adding large decoupling capacitances between the supply voltage and ground. However, situations may arise where reduction of series inductances and resistances cannot be accomplished. Therefore, to assist in controlling the transient current swings, reduction of clocking frequencies are performed in a controlled manner.
摘要翻译：提供了一种方法，装置和计算机程序以减少模式转换期间的瞬态电流摆动。传统上，芯片上的瞬态电源电压波动占大部分电源。串联电感和电阻的数量通常最小化，同时在电源电压和地之间增加大的去耦电容。然而，不能实现串联电感和电阻的降低的情况。因此，为了帮助控制瞬态电流摆动，以受控的方式执行时钟频率的降低。

8. 发明授权

US07392419B2 System and method automatically selecting intermediate power supply voltages for intermediate level shifters 失效
标题翻译：系统和方法自动选择中间电平转换器的中间电源电压
公开(公告)号：US07392419B2
公开(公告)日：2008-06-24
申请号：US11171756
申请日：2005-06-30
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

9. 发明申请

US20080143419A1 SYSTEM FOR AUTOMATICALLY SELECTING INTERMEDIATE POWER SUPPLY VOLTAGES FOR INTERMEDIATE LEVEL SHIFTERS 失效
标题翻译：用于自动选择中级电平变送器的中间电源电压的系统
公开(公告)号：US20080143419A1
公开(公告)日：2008-06-19
申请号：US12036936
申请日：2008-02-25
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

10. 发明授权

US07363178B2 Method and apparatus for measuring the relative duty cycle of a clock signal 有权
标题翻译：用于测量时钟信号的相对占空比的方法和装置
公开(公告)号：US07363178B2
公开(公告)日：2008-04-22
申请号：US11555018
申请日：2006-10-31
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi , Bin Wan
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi , Bin Wan
IPC分类号： G01R29/02
CPC分类号： G01R31/31922 , G01R29/0273 , G01R31/31725 , G01R31/31727
摘要： In one embodiment, the disclosed methodology and apparatus measure relative duty cycle information of a clock signal with respect to an input node as the clock signal travels to selected nodes of a clock distribution network on an electronic circuit. The apparatus operates in a benchmark mode to determine benchmark duty cycle information and then subsequently operates an a relative mode to determine relative duty cycle information of the clock signal at a selected node in comparison to the clock signal at an external input node.
摘要翻译：在一个实施例中，当时钟信号传播到电子电路上的时钟分配网络的选定节点时，所公开的方法和装置测量相对于输入节点的时钟信号的相对占空比信息。该装置在基准模式下操作以确定基准占空比信息，然后随后操作相对模式，以确定与外部输入节点处的时钟信号相比在所选节点处的时钟信号的相对占空比信息。

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