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1. 发明授权

US06529084B1 Interleaved feedforward VCO and PLL 有权
标题翻译：交错前馈VCO和PLL
公开(公告)号：US06529084B1
公开(公告)日：2003-03-04
申请号：US09974986
申请日：2001-10-11
申请人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Juan-Antonio Carballo , Gary Dale Carpenter , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03B524
CPC分类号： H03L7/0998 , H03K3/0315 , H03L7/0891 , H03L2207/06
摘要： A voltage controlled oscillator (VCO) and phase-locked loop (PLL) topologies that allow for low-voltage, high frequency, low-jitter operation are disclosed. The conventional PLL design is modified so as to bifurcate the error signal into AC and DC components. A VCO accepting AC- and DC-component control inputs adjusts its output frequency in accordance with both inputs.
摘要翻译：公开了一种允许低电压，高频，低抖动操作的压控振荡器（VCO）和锁相环（PLL）拓扑。传统的PLL设计被修改为将误差信号分成AC和DC分量。接受AC和DC分量控制输入的VCO根据两个输入调节其输出频率。

2. 发明授权

US06335650B1 Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages 有权
标题翻译：用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置
公开(公告)号：US06335650B1
公开(公告)日：2002-01-01
申请号：US09670829
申请日：2000-09-28
申请人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
发明人： David William Boerstler , Harm Peter Hofstee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03H1126
CPC分类号： H03K5/133 , H03K19/00384 , H03K19/018585 , H03K2005/0013
摘要： A method and apparatus for adjusting time delays in circuits with multiple operating supply voltages are disclosed. A voltage level detector and a delay means are coupled to a critical timing circuit of an integrated circuit capable of operating at multiple supply voltages. The voltage level detector detects a supply voltage at which the integrated circuit is operating. When the operating supply voltage of the integrated circuit changes from a first voltage level to a second voltage level, the voltage level detector sends a signal to the delay means and to a current enhancement circuit such that the delay means and current enhancement circuit can automatically modify the delay of the switching time of an output signal from the critical timing circuit.
摘要翻译：公开了一种用于调整具有多个工作电源电压的电路中的时间延迟的方法和装置。电压电平检测器和延迟装置耦合到能够在多个电源电压下工作的集成电路的关键定时电路。电压电平检测器检测集成电路正在工作的电源电压。当集成电路的工作电源电压从第一电压电平变化到第二电压电平时，电压电平检测器向延迟装置和当前增强电路发送信号，使得延迟装置和电流增强电路可以自动修改来自关键定时电路的输出信号的切换时间的延迟。

3. 发明授权

US06360238B1 Leading zero/one anticipator having an integrated sign selector 失效
标题翻译：领先的零/一个预测器具有集成的符号选择器
公开(公告)号：US06360238B1
公开(公告)日：2002-03-19
申请号：US09270469
申请日：1999-03-15
申请人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Kyung Tek Lee , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F501
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49936
摘要： A zero/one anticipator having an integrated sign selector is disclosed. A leading zeros string and a leading ones string are generated by examining carry propagates, generates, and kills of two adjacent bits of two input operands to an adder within a floating-point processor. The leading zeros string is for a positive sum, and the leading ones string is for a negative sum. A normalization shift amount is then determined from the leading zeros string and the leading ones string. A sign of a sum of the two input operands is then determined separately but concurrently with the normalization shift amount determination process. The sign is then utilized to select either the positive sum or the negative sum for a proper normalization shift amount.
摘要翻译：公开了具有集成符号选择器的零/一预测器。通过检查对浮点处理器内的加法器的两个输入操作数的两个相邻位进行传播，产生和杀死，产生前导零字符串和前导字符串。前导零字符串为正和，前导字符串为负数。然后从前导零字符串和前导字符串确定归一化偏移量。然后分别确定两个输入操作数的和的符号，但与归一化偏移量确定处理同时确定。然后，利用该符号来选择正和或负的正和归一化移位量。

4. 发明申请

US20090302929A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 有权
标题翻译：使用非对称双栅极器件中二极管电压的独立控制改变电源电压或参考电压的方法和装置
公开(公告)号：US20090302929A1
公开(公告)日：2009-12-10
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

5. 发明授权

US06175852B1 High-speed binary adder 失效
标题翻译：高速二进制加法器
公开(公告)号：US06175852B1
公开(公告)日：2001-01-16
申请号：US09114117
申请日：1998-07-13
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F750
CPC分类号： G06F7/508
摘要： A high-speed carry-lookahead binary adder is disclosed. The binary adder includes multiple rows of carry-lookahead circuits, a half-sum module, and a sum/carry module. A first carry-lookahead circuit row includes multiple eight-bit group generate circuits and multiple eight-bit group propagate circuits. Each of the eight-bit group generate circuits produces a generate signal for a corresponding bit location. Each of the eight-bit group propagate circuits produces a propagate signal for a corresponding bit location. The half-sum module is utilized to generate a half-sum signal. By utilizing the half-sum signal, the generate signals, and the propagate signals, the sum/carry module generates sum signals and a carry signal.
摘要翻译：公开了一种高速进位 - 前瞻二进制加法器。二进制加法器包括多行进位查找电路，半和模块和和/进位模块。第一进位 - 前瞻电路行包括多个8位组生成电路和多个8位组传播电路。八位组生成电路中的每一个产生相应位位置的生成信号。八位组传播电路中的每一个产生相应位位置的传播信号。半和模块用于产生半和信号。通过利用半和信号，生成信号和传播信号，和/进位模块产生和信号和进位信号。

6. 发明授权

US07952422B2 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US07952422B2
公开(公告)日：2011-05-31
申请号：US12511658
申请日：2009-07-29
申请人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K3/01
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

7. 发明申请

US20090303778A1 Methods and Apparatus for Varying a Supply Voltage or Reference Voltage Using Independent Control of Diode Voltage in Asymmetrical Double-Gate Devices 审中-公开
公开(公告)号：US20090303778A1
公开(公告)日：2009-12-10
申请号：US12511666
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G11C11/00
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.

8. 发明授权

US06282557B1 Low latency fused multiply-adder 失效
标题翻译：低延迟融合乘法加法器
公开(公告)号：US06282557B1
公开(公告)日：2001-08-28
申请号：US09207483
申请日：1998-12-08
申请人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
发明人： Sang Hoo Dhong , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G06F748
CPC分类号： G06F7/5443 , G06F7/5318
摘要： A low latency fused multiply-adder for adding a product of a first binary number and a second binary number to a third binary number is disclosed. The low latency fused multiply-adder includes a partial product generation module, a partial product reduction module, and a carry propagate adder. The partial product generation module generates a set of partial products from the first binary number and the second binary number. Coupled to the partial product generation module, the partial product reduction module combines the set of partial products with the third binary number to produce a redundant Sum and a redundant Carry. Finally, the carry propagate adder adds the redundant Sum and the redundant Carry to yield a Sum Total.
摘要翻译：公开了一种用于将第一二进制数和第二二进制数的乘积加到第三个二进制数的低延迟融合乘法加法器。低延迟融合乘法器包括部分乘积生成模块，部分乘积减少模块和进位传播加法器。部分乘积生成模块从第一二进制数和第二二进制数生成一组部分乘积。与部分产品生成模块相结合，部分产品减少模块将部分产品集合与第三个二进制数组合，以产生冗余Sum和冗余进位。最后，进位传播加法器将冗余Sum和冗余Carry相加，得到Sum Total。

9. 发明授权

US09076509B2 Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices 有权
标题翻译：使用不对称双栅极器件中二极管电压的独立控制来改变电源电压或参考电压的方法和装置
公开(公告)号：US09076509B2
公开(公告)日：2015-07-07
申请号：US12511666
申请日：2009-07-29
申请人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Ching-Te Kent Chuang , Keunwoo Kim , Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： G11C11/00 , G11C5/14 , G11C11/412 , G11C11/417
CPC分类号： G11C5/147 , G11C11/412 , G11C11/417
摘要： Methods and apparatus are provided for varying one or more of a supply voltage and reference voltage in an integrated circuit, using independent control of a diode voltage in an asymmetrical double-gate device. An integrated circuit is provided that is controlled by one or more of a supply voltage and a reference voltage. The integrated circuit comprises an independently controlled asymmetrical double-gate device to adjust one or more of the supply voltage and the reference voltage. The independent control may comprise, for example, a back gate bias. The independently controlled asymmetrical double-gate device may be employed in a number of applications, including voltage islands, static RAM, and to improve the power and performance of a processing unit.
摘要翻译：提供了用于在集成电路中改变电源电压和参考电压中的一个或多个的方法和装置，使用对不对称双栅极器件中的二极管电压的独立控制。提供由电源电压和参考电压中的一个或多个控制的集成电路。集成电路包括独立控制的非对称双栅极器件，用于调节电源电压和参考电压中的一个或多个。独立控制可以包括例如背栅偏置。独立控制的非对称双栅极器件可以用于包括电压岛，静态RAM在内的许多应用中，并且用于改善处理单元的功率和性能。

10. 发明授权

US07142015B2 Fast turn-off circuit for controlling leakage 失效
公开(公告)号：US07142015B2
公开(公告)日：2006-11-28
申请号：US10948444
申请日：2004-09-23
申请人： Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
发明人： Jente Benedict Kuang , Hung Cai Ngo , Kevin John Nowka
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/003 , H03K17/16
CPC分类号： H03K19/0013 , H03K19/01721
摘要： A buffer, logic circuit, and data processing system employing fast turn-off drive circuitry for reducing leakage. Leakage current in logic circuitry is managed by coupling and decoupling the voltage potentials applied to large, high-leakage devices. Circuitry includes a low leakage logic path for holding logic states of an output after turning off high-leakage devices. A fast turn-off logic path in parallel with the low leakage logic path is used to assert each logic state in the forward direction from input to output. The large output device in each fast turn-off path is relieved of leakage stress by asserting logic states at driver inputs that cause the driver to turn OFF after the output logic state has been asserted.

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