专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07747892B2 System for automatically selecting intermediate power supply voltages for intermediate level shifters 失效
标题翻译：用于自动选择中间电平转换器的中间电源电压的系统
公开(公告)号：US07747892B2
公开(公告)日：2010-06-29
申请号：US12036936
申请日：2008-02-25
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

2. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

3. 发明授权

US07350095B2 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US07350095B2
公开(公告)日：2008-03-25
申请号：US11082973
申请日：2005-03-17
申请人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/00 , G06F1/12 , G06F1/04
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

4. 发明授权

US07392419B2 System and method automatically selecting intermediate power supply voltages for intermediate level shifters 失效
标题翻译：系统和方法自动选择中间电平转换器的中间电源电压
公开(公告)号：US07392419B2
公开(公告)日：2008-06-24
申请号：US11171756
申请日：2005-06-30
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

5. 发明申请

US20080143419A1 SYSTEM FOR AUTOMATICALLY SELECTING INTERMEDIATE POWER SUPPLY VOLTAGES FOR INTERMEDIATE LEVEL SHIFTERS 失效
标题翻译：用于自动选择中级电平变送器的中间电源电压的系统
公开(公告)号：US20080143419A1
公开(公告)日：2008-06-19
申请号：US12036936
申请日：2008-02-25
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并且产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

6. 发明授权

US07917795B2 Digital circuit to measure and/or correct duty cycles 有权
标题翻译：用于测量和/或校正占空比的数字电路
公开(公告)号：US07917795B2
公开(公告)日：2011-03-29
申请号：US12014501
申请日：2008-01-15
申请人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Byron Lee Krauter , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/00 , G06F1/04 , H03K19/096 , H03K5/22 , H03K7/08 , H03K9/08 , H03L7/06 , G01R23/00 , G01M19/00
CPC分类号： G06F1/10 , H03K5/1565
摘要： A method, an apparatus, and a computer program are provided to measure and/or correct duty cycles. Duty cycles of various signals, specifically clocking signals, are important. However, measurement of very high frequency signals, off-chip, and in a laboratory environment can be very difficult and present numerous problems. To combat problems associated with making off-chip measurements and adjustments of signal duty cycles, comparisons are made between input signals and divided input signals that allow for easy measurement and adjustment of on-chip signals, including clocking signals.
摘要翻译：提供了一种方法，装置和计算机程序来测量和/或校正占空比。各种信号的占空比，特别是时钟信号是很重要的。然而，测量非常高频率的信号，芯片外和实验室环境可能是非常困难的并且存在许多问题。为了解决与片外测量和信号占空比调整相关的问题，可以比较输入信号和分频输入信号，从而便于测量和调整片上信号，包括时钟信号。

7. 发明申请

US20070300082A1 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US20070300082A1
公开(公告)日：2007-12-27
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry , Sang Hoo Dhong
IPC分类号： G06F1/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

8. 发明授权

US08736304B2 Self-biased high speed level shifter circuit 有权
标题翻译：自偏置高速电平转换电路
公开(公告)号：US08736304B2
公开(公告)日：2014-05-27
申请号：US11171758
申请日：2005-06-30
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03K19/0175
CPC分类号： H03K19/018507
摘要： A method and apparatus for translating signals between different components located in different power boundaries in a mixed voltage system. A level shifter system includes a first level shifter circuit connected to a first voltage source. A second level shifter circuit connects to a second voltage source. An intermediate level shifter circuit has an input that connects to the output of the first level shifter circuit. The output of the intermediate level shifter circuit connects to the input of the second level shifter circuit. The intermediate level shifter circuit uses an intermediate voltage source having an intermediate voltage about midway between the first voltage of the first voltage source and the second voltage of the second voltage source.
摘要翻译：一种用于在混合电压系统中位于不同功率边界的不同部件之间转换信号的方法和装置。电平移位器系统包括连接到第一电压源的第一电平移位器电路。第二电平移位器电路连接到第二电压源。中间电平移位器电路具有连接到第一电平移位器电路的输出的输入。中间电平移位器电路的输出连接到第二电平移位器电路的输入端。中间电平移位器电路使用具有在第一电压源的第一电压和第二电压源的第二电压之间的中间的中间电压的中间电压源。

9. 发明申请

US20070075764A1 Level shifter system and method to minimize duty cycle error due to voltage differences across power domains 失效
标题翻译：电平移位器系统和方法，可以最大限度地减少跨越电源域的电压差造成的占空比误差
公开(公告)号：US20070075764A1
公开(公告)日：2007-04-05
申请号：US11242670
申请日：2005-10-04
申请人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： H03L5/00
CPC分类号： H03K19/00384 , H03K5/1565 , H03K19/00323 , H03K19/00369 , H03K19/0175
摘要： The present invention provides for a system comprising a first stable voltage module configured to receive a first power supply from a first power supply domain and to generate a first stable voltage in response to the received first power supply. A second stable voltage module is configured to receive a second power supply from a second power supply domain and to generate a second stable voltage in response to the received second power supply. A first set of resistors is coupled to the first stable voltage module and configured in parallel. A second set of resistors is coupled to the second stable voltage module and configured in parallel. A set of capacitors is coupled in parallel to the first set of resistors and the second set of resistors and a plurality of level shifters are coupled to the second set of resistors.
摘要翻译：本发明提供了一种系统，其包括第一稳定电压模块，其被配置为从第一电源域接收第一电源并且响应于所接收的第一电源产生第一稳定电压。第二稳定电压模块被配置为从第二电源域接收第二电源并且响应于所接收的第二电源产生第二稳定电压。第一组电阻器耦合到第一稳定电压模块并且并联配置。第二组电阻器耦合到第二稳定电压模块并且并联配置。一组电容器并联耦合到第一组电阻器，并且第二组电阻器和多个电平移位器耦合到第二组电阻器。

10. 发明授权

US07176731B2 Variation tolerant charge leakage correction circuit for phase locked loops 失效
标题翻译：用于锁相环的变容差电荷泄漏校正电路
公开(公告)号：US07176731B2
公开(公告)日：2007-02-13
申请号：US10926596
申请日：2004-08-26
申请人： Franklin Manuel Baez , David William Boerstler , Eskinder Hailu , Kazuhiko Miki
发明人： Franklin Manuel Baez , David William Boerstler , Eskinder Hailu , Kazuhiko Miki
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/095
摘要： The present invention provides for compensation of leakage charge in a PLL. A first plurality and second plurality of charge pumps has a source charge pump and a sink charge pump, and each charge pump has its own switch. A first node is coupled between at least one source charge pump and at least one sink charge pump. A second node coupled between at least one source charge pump and at least one sink charge pump. A PLL filter is coupled to the first node. A dummy filter is coupled to the second node. A first input of a differential mode sensor is coupled to the PLL filter. A second input of a differential mode sensor is coupled to the dummy filter. A first input of a common mode sensor is coupled to the dummy filter. A second input of a common mode sensor coupled to the PLL filter.
摘要翻译：本发明提供了对PLL中的泄漏电荷的补偿。第一多个和第二多个电荷泵具有源电荷泵和吸收电荷泵，并且每个电荷泵具有其自己的开关。第一节点耦合在至少一个源电荷泵和至少一个电荷泵之间。耦合在至少一个源电荷泵和至少一个吸收电荷泵之间的第二节点。 PLL滤波器耦合到第一节点。虚拟滤波器耦合到第二节点。差分模式传感器的第一输入端耦合到PLL滤波器。差模传感器的第二输入端连接到虚拟滤波器。共模传感器的第一输入耦合到虚拟滤波器。耦合到PLL滤波器的共模传感器的第二输入。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式