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1. 发明授权

US06391769B1 Method for forming metal interconnection in semiconductor device and interconnection structure fabricated thereby 有权
标题翻译：用于在半导体器件中形成金属互连的方法和由此制造的互连结构
公开(公告)号：US06391769B1
公开(公告)日：2002-05-21
申请号：US09525154
申请日：2000-03-14
申请人： Jong-myeong Lee , Hyun-seok Lim , Byung-hee Kim , Gil-heyun Choi , Sang-in Lee
发明人： Jong-myeong Lee , Hyun-seok Lim , Byung-hee Kim , Gil-heyun Choi , Sang-in Lee
IPC分类号： H01L214763
CPC分类号： H01L21/76855 , H01L21/28562 , H01L21/32051 , H01L21/76843 , H01L21/76856 , H01L21/76876 , H01L21/76879 , H01L21/76882 , H01L21/76888 , H01L2221/1089
摘要： A method for forming a metal interconnection filling a contact hole or a groove having a high aspect ratio, and a contact structure fabricated thereby. An interdielectric layer pattern, having a recessed region serving as a contact hole, a via hole or a groove, is formed on a semiconductor substrate. A barrier metal layer is formed on the entire surface of the resultant structure where the interdielectric layer pattern is formed. An anti-nucleation layer is selectively formed only on the non-recessed region of the barrier metal layer. The anti-nucleation layer is formed by forming a metal layer overlying the barrier metal layer in regions other than the recessed region, and then spontaneously oxidizing the metal layer in a vacuum. Also, the anti-nucleation layer may be formed by in-situ forming the barrier metal layer and the metal layer and then oxidizing the metal layer by an annealing process. Subsequently, a metal plug is selectively formed in the recessed region, surrounded by the barrier metal layer, thereby forming a metal interconnection for completely filling the contact hole or the groove having a high aspect ratio. A metal liner may be formed instead of the metal plug, followed by forming a metal layer filling the region surrounded by the metal liner, thereby forming a metal interconnection for completely filling the contact hole or groove having a high aspect ratio.
摘要翻译：一种用于形成填充高纵横比的接触孔或槽的金属互连的方法，以及由此制造的接触结构。在半导体衬底上形成具有用作接触孔的凹陷区域，通孔或沟槽的电介质层图案。在形成介电层图案的所得结构的整个表面上形成阻挡金属层。仅在阻挡金属层的非凹陷区域选择性地形成抗成核层。通过在除了凹陷区域之外的区域中形成覆盖阻挡金属层的金属层，然后在真空中自发氧化金属层，形成抗成核层。此外，抗成核层可以通过原位形成阻挡金属层和金属层，然后通过退火处理来氧化金属层而形成。随后，在由阻挡金属层包围的凹陷区域中选择性地形成金属插塞，从而形成用于完全填充接触孔或具有高纵横比的沟槽的金属互连。可以形成金属衬垫而不是金属插塞，随后形成填充由金属衬垫包围的区域的金属层，从而形成用于完全填充具有高纵横比的接触孔或槽的金属互连。

2. 发明授权

US5665659A Method for forming metal layer of a semiconductor device 失效
标题翻译：用于形成半导体器件的金属层的方法
公开(公告)号：US5665659A
公开(公告)日：1997-09-09
申请号：US257420
申请日：1994-06-09
申请人： Sang-in Lee , Gil-heyun Choi , Young-soo Jeon
发明人： Sang-in Lee , Gil-heyun Choi , Young-soo Jeon
IPC分类号： H01L21/28 , C23C14/04 , C23C14/58 , H01L21/285 , H01L21/321 , H01L21/768 , C23C14/34 , H01L21/324 , H01L21/44
CPC分类号： C23C14/5806 , C23C14/046 , H01L21/28512 , H01L21/321 , H01L21/76843 , H01L21/76856 , H01L21/76864 , H01L21/76877
摘要： A method for forming a metal layer including the steps of heat treating a semiconductor substrate for a predetermined time at an intermediate temperature between 200.degree. C. and 400.degree. C., then depositing the metal layer on the semiconductor substrate at a temperature below 200.degree. C., in a vacuum, then thermally treating the metal layer at a temperature between 0.6 Tm-1.0 Tm (where Tm is the melting point of the metal layer), without breaking the vacuum, thereby reflowing the grains of the metal layer, and then gradually cooling the metal layer. Alternatively, the intermediate heat-treatment step can be performed after the metal layer is thermally treated, in which case, the metal layer should thereafter be rapidly cooled.
摘要翻译：一种用于形成金属层的方法，包括以下步骤：在200℃至400℃的中间温度下将半导体衬底热处理预定时间，然后在低于200℃的温度下将金属层沉积在半导体衬底上在真空中，然后在0.6Tm -1.0Tm（其中Tm是金属层的熔点）的温度下对金属层进行热处理，而不破坏真空，从而回流金属层的晶粒，以及然后逐渐冷却金属层。或者，中间热处理步骤可以在金属层被热处理之后进行，在这种情况下，金属层此后应该被快速冷却。

3. 发明授权

US5843843A Method for forming a wiring layer a semiconductor device 失效
标题翻译：用于形成半导体器件的布线层的方法
公开(公告)号：US5843843A
公开(公告)日：1998-12-01
申请号：US743916
申请日：1996-11-05
申请人： Sang-in Lee , Gil-heyun Choi
发明人： Sang-in Lee , Gil-heyun Choi
IPC分类号： H01L21/768 , H01L21/28 , H01L21/30 , H01L21/3205 , H01L21/762 , H01L21/822 , H01L23/52 , H01L27/04 , H01L21/441
CPC分类号： H01L21/3003 , H01L21/76202 , H01L21/76843 , H01L21/76856 , H01L21/76858 , H01L21/76862 , H01L21/76877
摘要： A method for forming wiring layer of a semiconductor device for improving the step coverage and filling of the contact hole is disclosed. After forming an underlayer of the wiring layer on a semiconductor substrate, the surface of the underlayer is hydrogen-treated by exposing the underlayer to hydrogen plasma or hydrogen radicals to thereby H-terminate the surface portion of the underlayer. Thus, the characteristics of the underlying layer is improved. When depositing a metal such aluminum or aluminum alloy on the underlayer to thereby form a first conductive layer, large grains of the deposited metal are obtained. The step coverage of the deposited metal layer is enhanced and the mobility of the metal grains is increased. When sputtering the metal at a high temperature or when heat-treating the metal layer which has been formed at a low temperature, the filling of the metal into the contact hole is improved.
摘要翻译：公开了一种用于形成半导体器件的布线层的方法，用于改善台阶覆盖和接触孔的填充。在半导体衬底上形成布线层的底层之后，通过将底层暴露于氢等离子体或氢自由基来对底层的表面进行氢处理，从而使底层的表面部分H终止。因此，底层的特性得到改善。当在底层上沉积诸如铝或铝合金的金属从而形成第一导电层时，获得沉积金属的大颗粒。沉积的金属层的台阶覆盖率增加，并且金属颗粒的迁移率增加。当在高温下溅射金属时，或者当在低温下形成的金属层进行热处理时，金属填充到接触孔中得到改善。

4. 发明授权

US06372598B1 Method of forming selective metal layer and method of forming capacitor and filling contact hole using the same 有权
公开(公告)号：US06372598B1
公开(公告)日：2002-04-16
申请号：US09334588
申请日：1999-06-16
申请人： Sang-bum Kang , Yun-sook Chae , Sang-in Lee , Hyun-seok Lim , Mee-young Yoon
发明人： Sang-bum Kang , Yun-sook Chae , Sang-in Lee , Hyun-seok Lim , Mee-young Yoon
IPC分类号： H01L2120
摘要： A selective metal layer formation method, a capacitor formation method using the same, and a method of forming an ohmic layer on a contact hole and filling the contact hole using the same, are provided. A sacrificial metal layer is selectively deposited on a conductive layer by supplying a sacrificial metal source gas which deposits selectively on a semiconductor substrate having an insulating film and the conductive layer. Sacrificial metal atoms and a halide are formed, and the sacrificial metal layer is replaced with a deposition metal layer such as titanium Ti or platinum Pt, by supplying a metal halide gas having a halogen coherence smaller than the halogen coherence of the metal atoms in the sacrificial metal layer. If such a process is used to form a capacitor lower electrode or form an ohmic layer on the bottom of a contact hole, a metal layer can be selectively formed at a temperature of 500° C. or lower.

5. 发明授权

US6144060A Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature 失效
标题翻译：其中具有缓冲层的集成电路器件含有通过在低温下热处理而稳定的金属氧化物
公开(公告)号：US6144060A
公开(公告)日：2000-11-07
申请号：US127353
申请日：1998-07-31
申请人： In-seon Park , Yeong-kwan Kim , Sang-in Lee , Byung-hee Kim , Sang-min Lee , Chang-soo Park
发明人： In-seon Park , Yeong-kwan Kim , Sang-in Lee , Byung-hee Kim , Sang-min Lee , Chang-soo Park
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/285 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/10852 , H01L28/55
摘要： Integrated circuit devices include a first dielectric layer, an electrically insulating layer on the first dielectric layer and an an aluminum oxide buffer layer formed by atomic layer deposition (ALD) and stabilized by heat treatment at a temperature of less than about 600.degree. C., between the first dielectric layer and the electrically insulating layer. The first dielectric layer may comprise a high dielectric material such as a ferroelectric or paraelectric material. The electrically insulating layer may also comprise a material selected from the group consisting of silicon dioxide, borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). To provide a preferred integrated circuit capacitor, a substrate may be provided and an interlayer dielectric layer may be provided on the substrate. Here, a metal layer may also be provided between the interlayer dielectric layer and the first dielectric layer. The metal layer may comprise a material selected from the group consisting of Pt, Ru, Ir, and Pd.
摘要翻译：集成电路器件包括第一电介质层，第一电介质层上的电绝缘层和通过原子层沉积（ALD）形成并通过在小于约600℃的温度下进行热处理而稳定的氧化铝缓冲层，在第一介电层和电绝缘层之间。第一电介质层可以包括高电介质材料，例如铁电或顺电材料。电绝缘层还可以包括选自二氧化硅，硼磷硅酸盐玻璃（BPSG）和磷硅玻璃（PSG）的材料。为了提供优选的集成电路电容器，可以提供衬底，并且可以在衬底上提供层间电介质层。这里，还可以在层间介电层和第一介电层之间设置金属层。金属层可以包括选自Pt，Ru，Ir和Pd的材料。

6. 发明申请

US20060020956A1 Data recording/reproducing apparatus 有权
标题翻译：数据记录/重放装置
公开(公告)号：US20060020956A1
公开(公告)日：2006-01-26
申请号：US11185876
申请日：2005-07-21
申请人： Sang-in Lee
发明人： Sang-in Lee
IPC分类号： G11B33/12 , G11B15/68
CPC分类号： G06F1/184 , G06F1/187 , G11B25/10 , G11B33/022 , G11B33/027
摘要： A data recording/reproducing apparatus, includes: an open front housing having a base frame and a cover frame; a recording/reproducing unit installed in the housing to record/reproduce data in/from a predetermined recording medium; a circuit board installed parallel to the recording/reproducing unit in the housing; a front unit connected to the open front of the housing to support operation buttons; a first locking unit which locks the front unit and the recording/reproducing unit; and a second locking unit which locks the front unit and the housing at a position corresponding to the circuit board.
摘要翻译：一种数据记录/再现装置，包括：具有基架和盖框架的敞开前壳; 安装在壳体中以在预定记录介质中记录/再现数据的记录/再现单元; 与壳体中的记录/再现单元平行安装的电路板; 连接到所述壳体的敞开前部以支撑操作按钮的前部单元; 第一锁定单元，其锁定前单元和记录/再现单元; 以及第二锁定单元，其将前单元和壳体锁定在对应于电路板的位置。

7. 发明授权

US06284591B1 Formation method of interconnection in semiconductor device 有权
标题翻译：半导体器件互连的形成方法
公开(公告)号：US06284591B1
公开(公告)日：2001-09-04
申请号：US09299566
申请日：1999-04-27
申请人： Sang-in Lee
发明人： Sang-in Lee
IPC分类号： H01L218242
CPC分类号： H01L27/10873 , H01L27/1052
摘要： A method of forming an interconnection by using a landing pad is disclosed. In a semiconductor device having a memory cell portion and a peripheral circuit portion, a refractory metal is used for the bitline instead of the usual polycide, to concurrently form a contact on an active region of an N-type and a P-type substrate. A landing pad is formed on the peripheral circuit portion at the same time as a bitline is formed on the memory cell portion. In such a process, a substantial contact hole for the interconnection is formed on the landing pad so that an aspect ratio of the contact can be lowered. Accordingly, when forming a metal interconnection, the contact hole for the interconnection is easily filled by Al-reflow so that the step coverage of the metal being deposited in the contact hole for the interconnection is enhanced, and the contact resistance is reduced. As a result, the reliability of the semiconductor device is improved.
摘要翻译：公开了一种通过使用着陆垫形成互连的方法。在具有存储单元部分和外围电路部分的半导体器件中，难题金属用于位线而不是通常的多硅化物，以在N型和P型衬底的有源区上同时形成接触。在存储单元部分上形成位线的同时，在外围电路部分上形成着键盘。在这种过程中，用于互连的实质接触孔形成在着陆焊盘上，使得可以降低接触的纵横比。因此，当形成金属互连时，易于通过Al回流填充用于互连的接触孔，使得沉积在用于互连的接触孔中的金属的台阶覆盖增强，并且接触电阻降低。结果，提高了半导体器件的可靠性。

8. 发明授权

US06207487B1 Method for forming dielectric film of capacitor having different thicknesses partly 失效
标题翻译：部分形成不同厚度的电容器的电介质膜的形成方法
公开(公告)号：US06207487B1
公开(公告)日：2001-03-27
申请号：US09415830
申请日：1999-10-12
申请人： Yeong-kwan Kim , Sang-in Lee , Chang-soo Park , Young-sun Kim
发明人： Yeong-kwan Kim , Sang-in Lee , Chang-soo Park , Young-sun Kim
IPC分类号： H01L218244
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/0228 , H01L21/31604 , H01L21/3162 , H01L21/31691 , H01L28/55
摘要： The present invention discloses a method for forming a dielectric film having improved leakage current characteristics in a capacitor. A lower electrode having a surface and a rounded protruding portion is formed on a semiconductor substrate. The surface and the protruding portion define at least one concave area. A chemisorption layer is then formed on the surface and the rounded protruding portion by supplying a first reactant. Also, a physisorption layer is formed on the chemisorption layer from the first reactant. Next, a portion of the physisorption layer is removed and a portion of the physisorption layer is left on the concave area. Subsequently, the chemisorption layer and the portion of the physisorption layer on the concave area react with a second reactant to form a dielectric film on the surface of the lower electrode. The thickness of said dielectric film is greater on the concave area than on the protruding portion, thereby reducing leakage current.
摘要翻译：本发明公开了一种在电容器中形成具有改善的漏电流特性的电介质膜的方法。在半导体衬底上形成具有表面和圆形突出部分的下电极。表面和突出部分限定至少一个凹入区域。然后通过提供第一反应物在表面和圆形突出部分上形成化学吸附层。此外，在第一反应物的化学吸附层上形成物理吸附层。接下来，去除一部分物理吸附层，并将一部分物理吸附层留在凹面上。随后，化学吸收层和凹面上的物理吸附层的部分与第二反应物反应，以在下电极的表面上形成电介质膜。所述电介质膜的厚度在凹区域上大于突出部分的厚度，从而减少漏电流。

9. 发明授权

US6087257A Methods of fabricating a selectively deposited tungsten nitride layer and metal wiring using a tungsten nitride layer 失效
标题翻译：使用氮化钨层制造选择性沉积的氮化钨层和金属布线的方法
公开(公告)号：US6087257A
公开(公告)日：2000-07-11
申请号：US751153
申请日：1996-11-15
申请人： Byung-lyul Park , Jung-min Ha , Dae-hong Ko , Sang-in Lee
发明人： Byung-lyul Park , Jung-min Ha , Dae-hong Ko , Sang-in Lee
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76855 , H01L21/76843 , H01L21/76879
摘要： Methods for fabricating a tungsten nitride layer in a semiconductor substrate having an insulating layer formed thereon. The methods include forming a contact hole through the insulating layer. A tungsten nitride layer is then selectively deposited only in the contact hole by selectively reacting a nitrogen-containing gas with a tungsten source gas so as to prevent formation of tungsten nitride layer on the insulating layer outside the contact hole. Methods or fabricating metal wiring utilizing the methods of fabricating a tungsten nitride layer are also provided.
摘要翻译：在其上形成有绝缘层的半导体衬底中制造氮化钨层的方法。所述方法包括形成穿过绝缘层的接触孔。然后通过选择性地使含氮气体与钨源气体反应来选择性地沉积氮化钨层，以防止在接触孔外部的绝缘层上形成氮化钨层。还提供了利用制造氮化钨层的方法或制造金属布线的方法。

10. 发明授权

US5998870A Wiring structure of semiconductor device and method for manufacturing the same 失效
标题翻译：半导体装置的配线结构及其制造方法
公开(公告)号：US5998870A
公开(公告)日：1999-12-07
申请号：US873869
申请日：1997-06-12
申请人： Sang-in Lee , Sun-ho Ha
发明人： Sang-in Lee , Sun-ho Ha
IPC分类号： H01L21/28 , H01L21/285 , H01L21/768 , H01L23/522 , H01L23/532 , H01L21/44
CPC分类号： H01L21/76876 , H01L21/28518 , H01L21/76838 , H01L21/76843 , H01L21/76855 , H01L21/76862 , H01L21/76865 , H01L21/76882 , Y10S257/915
摘要： A wiring structure of a semiconductor device buries an aperture, for example, a contact hole or via hole. The wiring structure includes a semiconductor substrate, an insulating layer formed on the semiconductor substrate and having an aperture formed therein, a diffusion barrier film formed on the inner sidewalls of the aperture and which has a smooth surface without having grain boundaries made of a refractory metal or refractory metal compound, and a metal layer formed on the diffusion barrier film. The metal layer formed on the smooth sidewalls of the diffusion barrier film is made of a uniformly and continuously formed aluminum film having an excellent step coverage. Accordingly, the method for forming the wiring structure effectively buries a contact hole having a high aspect ratio and enhances the reliability of a manufactured device.
摘要翻译：半导体器件的布线结构掩埋孔，例如接触孔或通孔。布线结构包括半导体衬底，形成在半导体衬底上并具有形成在其中的孔的绝缘层，形成在孔的内侧壁上并且具有光滑表面而不具有由难熔金属制成的晶界的扩散阻挡膜或难熔金属化合物，以及形成在扩散阻挡膜上的金属层。形成在扩散阻挡膜的平滑侧壁上的金属层由均匀且连续形成的具有优异的台阶覆盖率的铝膜制成。因此，用于形成布线结构的方法有效地掩盖了具有高纵横比的接触孔，并提高了所制造的器件的可靠性。

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