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1. 发明授权

US5656337A Method of forming a dielectric layer 失效
标题翻译：形成电介质层的方法
公开(公告)号：US5656337A
公开(公告)日：1997-08-12
申请号：US296931
申请日：1994-08-31
申请人： In-Seon Park , Myoung-Bum Lee , Chang-Gee Hong , Chang-Gyu Kim , U-In Chung
发明人： In-Seon Park , Myoung-Bum Lee , Chang-Gee Hong , Chang-Gyu Kim , U-In Chung
IPC分类号： H01L21/205 , C23C16/02 , C23C16/40 , C23C16/44 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/3205 , H05H1/00
CPC分类号： H01L21/02164 , C23C16/0245 , C23C16/402 , C23C16/44 , H01L21/02271 , H01L21/02315 , H01L21/31051 , H01L21/31608
摘要： A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.
摘要翻译：介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。沉积和平坦化可以在低温下进行并且在工艺上被简化。

2. 发明授权

US06489214B2 Method for forming a capacitor of a semiconductor device 有权
标题翻译：用于形成半导体器件的电容器的方法
公开(公告)号：US06489214B2
公开(公告)日：2002-12-03
申请号：US09962327
申请日：2001-09-26
申请人： Yeong-kwan Kim , In-seon Park , Sang-min Lee , Chang-soo Park
发明人： Yeong-kwan Kim , In-seon Park , Sang-min Lee , Chang-soo Park
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/02337 , H01L21/3162
摘要： A capacitor having high capacitance using a silicon-containing conductive layer as a storage node, and a method for forming the same, are provided. The capacitor includes a storage node, an amorphous Al2O3 dielectric layer, and a plate node. The amorphous Al2O3 layer is formed by a method in which reactive vapor phase materials are supplied on the storage node, for example, an atomic layered deposition method. Also, the storage node is processed by rapid thermal nitridation before forming the amorphous Al2O3 layer. The amorphous Al2O3 layer is densified by annealing at approximately 850° C. after forming a plate node, to thereby realize the equivalent thickness of an oxide layer which approximates a theoretical value of 30 Å.
摘要翻译：提供一种使用含硅导电层作为存储节点具有高电容的电容器及其形成方法。电容器包括存储节点，非晶Al 2 O 3介电层和板状节点。通过在存储节点上提供反应性气相材料的方法，例如原子层状沉积法，形成无定形Al 2 O 3层。此外，在形成无定形Al 2 O 3层之前，通过快速热氮化处理存储节点。通过在形成板状节点之后在约850℃下进行退火来致密化非晶Al 2 O 3层，从而实现近似理论值的氧化物层的等效厚度。

3. 发明授权

US6077772A Methods of forming metal interconnections including thermally treated barrier layers 有权
标题翻译：形成包括热处理阻挡层的金属互连的方法
公开(公告)号：US6077772A
公开(公告)日：2000-06-20
申请号：US270174
申请日：1999-03-16
申请人： In-Seon Park , Sung-Tae Kim , Du-Hwan Lee , Won-Goo Hur
发明人： In-Seon Park , Sung-Tae Kim , Du-Hwan Lee , Won-Goo Hur
IPC分类号： H01L21/768 , H01L21/4763
CPC分类号： H01L21/76856 , H01L21/76843 , H01L21/76882
摘要： A method of forming a metal interconnection includes the steps of forming a first conductive layer on a substrate, and forming an insulating layer on the first conductive layer and on the substrate. A contact hole is formed in the insulating layer thereby exposing a portion of the first conductive layer, a barrier layer is formed on the exposed portion of the first conductive layer in the contact hole, and a thermal treatment is performed on the barrier layer. After the step of performing the thermal treatment, a wetting layer is formed on a sidewall of the contact hole, and a second conductive layer is formed on the barrier layer and on the wetting layer in the contact hole.
摘要翻译：形成金属互连的方法包括以下步骤：在衬底上形成第一导电层，并在第一导电层和衬底上形成绝缘层。在绝缘层中形成接触孔，从而露出第一导电层的一部分，在接触孔中的第一导电层的暴露部分上形成阻挡层，并对阻挡层进行热处理。在进行热处理的步骤之后，在接触孔的侧壁上形成润湿层，并且在阻挡层和接触孔中的润湿层上形成第二导电层。

4. 发明授权

US6046927A Nonvolatile semiconductor memory device, a method of fabricating the same, and read, erase write methods of the same 有权
标题翻译：非易失性半导体存储器件，其制造方法以及其读取，擦除写入方法
公开(公告)号：US6046927A
公开(公告)日：2000-04-04
申请号：US177569
申请日：1998-10-23
申请人： Jong-ho Lee , In-Seon Park , Cha-Young Yoo
发明人： Jong-ho Lee , In-Seon Park , Cha-Young Yoo
IPC分类号： H01L27/108 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L27/105
CPC分类号： G11C11/22
摘要： A ferroelectric memory device includes a silicon-on-insulator substrate having a handling wafer, a first insulating layer, and a semiconductor layer. It also includes a first conductive layer used as a bit line formed in the first insulating layer, a source region formed in the semiconductor layer, a drain region formed in the semiconductor layer, a second insulating layer formed over the semiconductor layer between the source and drain regions, a second conductive layer for use as both a lower electrode and gate electrode, formed over the second insulating layer between the source and drain regions, a ferroelectric layer formed over the semiconductor layer, and a third conductive layer for use as an upper electrode formed over the ferroelectric layer. For reading, writing, and erasing, different voltages are applied to the upper electrode and the semiconductor layer between the drain and source. For writing, the upper electrode receives a writing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state to either invert polarization of the ferroelectric layer or retain initial polarization, depending upon the data. For erasing, the upper electrode receives an erasing voltage, and the semiconductor layer receives a ground voltage. This brings the drain and source to a floating state. For reading, the upper electrode receives a reading voltage, and the semiconductor layer receives a ground voltage. A sensing current is then provided to the drain, and potential variation is sensed on the bit line.
摘要翻译：铁电存储器件包括具有处理晶片，第一绝缘层和半导体层的绝缘体上硅衬底。它还包括用作形成在第一绝缘层中的位线的第一导电层，形成在半导体层中的源极区，形成在半导体层中的漏极区，在半导体层之间形成的第二绝缘层，漏极区域，用作下电极和栅电极的第二导电层，形成在源区和漏区之间的第二绝缘层上，形成在半导体层上的铁电层，以及用作上层的第三导电层形成在铁电层上的电极。对于读取，写入和擦除，不同的电压施加到漏极和源极之间的上部电极和半导体层。对于写入，上部电极接收写入电压，并且半导体层接收地电压。这取决于数据，将漏极和源极引入浮置状态以反转铁电层的极化或保持初始极化。为了擦除，上部电极接收擦除电压，半导体层接收接地电压。这将使排水和源处于浮动状态。为了读取，上部电极接收读取电压，半导体层接收接地电压。然后将感测电流提供给漏极，并且在位线上感测到电位变化。

5. 发明授权

US5096847A Method making an ultra high density DRAM cell with stacked capacitor 失效
标题翻译：使用堆叠电容器制造超高密度DRAM单元的方法
公开(公告)号：US5096847A
公开(公告)日：1992-03-17
申请号：US489820
申请日：1990-03-09
申请人： In-seon Park , Su-han Choi
发明人： In-seon Park , Su-han Choi
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/40
摘要： An ultra high integration DRAM cell and a method of manufacturing therefor are provided which increases the capacitance of the cell capacitor. The plate electrode consists of the second and fourth polycrystalline silicon layers; the storage electrode consists of the third polycrystalline silicon layer; the dielectric layer is increased by the area of the first dielectric layer.
摘要翻译：提供了一种超高集成度DRAM单元及其制造方法，其增加了单元电容器的电容。平板电极由第二和第四多晶硅层组成; 存储电极由第三多晶硅层组成; 电介质层增加第一电介质层的面积。

6. 发明授权

US06335240B1 Capacitor for a semiconductor device and method for forming the same 有权
公开(公告)号：US06335240B1
公开(公告)日：2002-01-01
申请号：US09226006
申请日：1999-01-06
申请人： Yeong-kwan Kim , In-seon Park , Sang-min Lee , Chang-soo Park
发明人： Yeong-kwan Kim , In-seon Park , Sang-min Lee , Chang-soo Park
IPC分类号： H01L218242
CPC分类号： H01L28/40 , H01L21/02178 , H01L21/0228 , H01L21/02304 , H01L21/02337 , H01L21/3162
摘要： A capacitor having high capacitance using a silicon-containing conductive layer as a storage node, and a method for forming the same, are provided. The capacitor includes a storage node, an amorphous Al2O3 dielectric layer, and a plate node. The amorphous Al2O3 layer is formed by a method in which reactive vapor phase materials are supplied on the storage node, for example, an atomic layered deposition method. Also, the storage node is processed by rapid thermal nitridation before forming the amorphous Al2O3 layer. The amorphous Al2O3 layer is densified by annealing at approximately 850° C. after forming a plate node, to thereby realize the equivalent thickness of an oxide layer which approximates a theoretical value of 30 Å.

7. 发明授权

US5814556A Method of filling a contact hole in a semiconductor substrate with a metal 失效
标题翻译：用金属填充半导体衬底中的接触孔的方法
公开(公告)号：US5814556A
公开(公告)日：1998-09-29
申请号：US698372
申请日：1996-08-15
申请人： Young-jin Wee , In-seon Park , Sang-in Lee
发明人： Young-jin Wee , In-seon Park , Sang-in Lee
IPC分类号： H01L21/285 , H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/76877
摘要： A method for forming a metal layer of an ultra-thin film according to metal deposition conditions and a method for forming metal wiring by filling a high aspect-ratio contact hole using cooling step prior to depositing the metal layer. In particular, the additional cooling process is performed before the process of depositing the metal layer and then the deposition process is performed in a state where the temperature of the wafer has been cooled down to a temperature in the range between -25.degree. C. and room temperature. The surface morphology of the deposited metal layer is improved and a continuous ultra-thin film can be obtained. Also, the aluminum filling characteristics in the contact hole having a high aspect-ratio are improved.
摘要翻译：根据金属沉积条件形成超薄膜的金属层的方法以及通过在沉积金属层之前使用冷却步骤填充高纵横比接触孔来形成金属布线的方法。特别地，在沉积金属层的过程之前进行附加的冷却过程，然后在晶片的温度已经冷却到-25℃和-25℃之间的温度的状态下进行沉积工艺，并且室内温度。沉积金属层的表面形态得到改善，可获得连续的超薄膜。此外，具有高纵横比的接触孔中的铝填充特性得到改善。

8. 发明授权

US6144060A Integrated circuit devices having buffer layers therein which contain metal oxide stabilized by heat treatment under low temperature 失效
标题翻译：其中具有缓冲层的集成电路器件含有通过在低温下热处理而稳定的金属氧化物
公开(公告)号：US6144060A
公开(公告)日：2000-11-07
申请号：US127353
申请日：1998-07-31
申请人： In-seon Park , Yeong-kwan Kim , Sang-in Lee , Byung-hee Kim , Sang-min Lee , Chang-soo Park
发明人： In-seon Park , Yeong-kwan Kim , Sang-in Lee , Byung-hee Kim , Sang-min Lee , Chang-soo Park
IPC分类号： H01L21/8247 , H01L21/02 , H01L21/285 , H01L21/822 , H01L21/8242 , H01L21/8246 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792 , H01L29/72
CPC分类号： H01L28/75 , H01L21/28568 , H01L27/10852 , H01L28/55
摘要： Integrated circuit devices include a first dielectric layer, an electrically insulating layer on the first dielectric layer and an an aluminum oxide buffer layer formed by atomic layer deposition (ALD) and stabilized by heat treatment at a temperature of less than about 600.degree. C., between the first dielectric layer and the electrically insulating layer. The first dielectric layer may comprise a high dielectric material such as a ferroelectric or paraelectric material. The electrically insulating layer may also comprise a material selected from the group consisting of silicon dioxide, borophosphosilicate glass (BPSG) and phosphosilicate glass (PSG). To provide a preferred integrated circuit capacitor, a substrate may be provided and an interlayer dielectric layer may be provided on the substrate. Here, a metal layer may also be provided between the interlayer dielectric layer and the first dielectric layer. The metal layer may comprise a material selected from the group consisting of Pt, Ru, Ir, and Pd.
摘要翻译：集成电路器件包括第一电介质层，第一电介质层上的电绝缘层和通过原子层沉积（ALD）形成并通过在小于约600℃的温度下进行热处理而稳定的氧化铝缓冲层，在第一介电层和电绝缘层之间。第一电介质层可以包括高电介质材料，例如铁电或顺电材料。电绝缘层还可以包括选自二氧化硅，硼磷硅酸盐玻璃（BPSG）和磷硅玻璃（PSG）的材料。为了提供优选的集成电路电容器，可以提供衬底，并且可以在衬底上提供层间电介质层。这里，还可以在层间介电层和第一介电层之间设置金属层。金属层可以包括选自Pt，Ru，Ir和Pd的材料。

9. 发明授权

US5560778A Apparatus for forming a dielectric layer 失效
标题翻译：用于形成电介质层的装置
公开(公告)号：US5560778A
公开(公告)日：1996-10-01
申请号：US465015
申请日：1995-06-05
申请人： In-Seon Park , Myoung-Bum Lee , Chang-Gee Hong , Chang-Gyu Kim , U-In Chung
发明人： In-Seon Park , Myoung-Bum Lee , Chang-Gee Hong , Chang-Gyu Kim , U-In Chung
IPC分类号： H01L21/205 , C23C16/02 , C23C16/40 , C23C16/44 , H01L21/31 , H01L21/3105 , H01L21/316 , H01L21/3205 , C23C16/00
CPC分类号： H01L21/02164 , C23C16/0245 , C23C16/402 , C23C16/44 , H01L21/02271 , H01L21/02315 , H01L21/31051 , H01L21/31608
摘要： A deposition rate of a dielectric material is varied with the electrical polarity of an underlying layer to obtain excellent deposition and planarization characteristics. A conductive layer and the underlying dielectric are surface-treated to have different electrical polarities so that the dielectric is formed by using the difference of deposition rates of the dielectric material between that on the conductive layer and that on the underlying dielectric. A CVD apparatus having a DC power source connected between a susceptor and a gas injection portion thereof is provided. The deposition and planarization can be performed at low temperatures and are simplified in process.
摘要翻译：介电材料的沉积速率随着下层的电极性而变化，以获得优异的沉积和平坦化特性。导电层和下面的电介质被表面处理以具有不同的电极性，使得通过使用电介质材料在导电层上和在下面的电介质之间的沉积速率的差异来形成电介质。提供了一种具有连接在基座和其气体注入部分之间的直流电源的CVD装置。沉积和平坦化可以在低温下进行并且在工艺上被简化。

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