专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07486574B2 Row active control circuit of pseudo static ranom access memory 失效
标题翻译：伪静态随机存取存储器的行主动控制电路
公开(公告)号：US07486574B2
公开(公告)日：2009-02-03
申请号：US11074894
申请日：2005-03-09
申请人： Jong Yeol Yang , Yin Jae Lee
发明人： Jong Yeol Yang , Yin Jae Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C2211/4065 , G11C2211/4067
摘要： A row active control circuit of a PSRAM controls a refresh timing when a refresh operation is performed before activation of a row path for embodiment of a page mode, thereby preventing mis-operations. The row active signal generating unit generates a row active signal when an active condition is set by the internal active signal. The internal active signal generating unit generates the internal active signal in response to a refresh start signal. The row active control unit generates a row active standby signal with the row active signal in response to the internal active signal. The external active signal generating unit for generating an external active control signal in response to the row active standby signal.
摘要翻译： PSRAM的行主动控制电路控制在页面模式的实施例的行路径激活之前执行刷新操作时的刷新定时，从而防止错误操作。当由内部有效信号设置有效状态时，行有源信号产生单元产生行有效信号。内部有源信号产生单元响应于刷新开始信号产生内部有效信号。行有源控制单元响应于内部有效信号产生具有行有源信号的行活动待机信号。外部有源信号产生单元，用于响应于行活动待机信号产生外部主动控制信号。

2. 发明授权

US08477559B2 Burst termination control circuit and semiconductor memory using the same 有权
标题翻译：突发终端控制电路和使用其的半导体存储器
公开(公告)号：US08477559B2
公开(公告)日：2013-07-02
申请号：US13408701
申请日：2012-02-29
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G11C8/18
CPC分类号： G11C7/1018
摘要： A semiconductor memory device includes a burst termination control unit and a data output control unit. The burst termination control unit generates a termination control signal, a read command, a write command and a mode resister read command. The data output control unit stops a data output operation in response to the termination control signal.
摘要翻译：半导体存储器件包括突发终止控制单元和数据输出控制单元。脉冲串终止控制单元生成终止控制信号，读取命令，写入命令和模式寄存器读取命令。数据输出控制单元响应于终止控制信号停止数据输出操作。

3. 发明授权

US08036045B2 Data output control circuit 有权
标题翻译：数据输出控制电路
公开(公告)号：US08036045B2
公开(公告)日：2011-10-11
申请号：US12315025
申请日：2008-11-26
申请人： Joo Hyeon Lee , Yin Jae Lee
发明人： Joo Hyeon Lee , Yin Jae Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/1045 , G11C7/1006 , G11C7/1012
摘要： A data output control circuit in a semiconductor memory device includes a driving signal generating unit configured to decode first and second I/O mode signals and first and second address level signals in response to a bank active signal and generate driving signals, and a data output multiplexing unit configured to output data signals of global I/O lines as multiplexing signals in response to the driving signals.
摘要翻译：半导体存储器件中的数据输出控制电路包括：驱动信号生成单元，被配置为响应于存储体有效信号来解码第一和第二I / O模式信号以及第一和第二地址电平信号，并产生驱动信号，以及数据输出复用单元，被配置为响应于驱动信号，将全局I / O线的数据信号作为多路复用信号输出。

4. 发明申请

US20100085819A1 Burst length control circuit and semiconductor memory device using the same 失效
标题翻译：突发长度控制电路和使用其的半导体存储器件
公开(公告)号：US20100085819A1
公开(公告)日：2010-04-08
申请号：US12319063
申请日：2008-12-30
申请人： Joo Hyeon Lee , Yin Jae Lee
发明人： Joo Hyeon Lee , Yin Jae Lee
IPC分类号： G11C7/00 , G11C8/18
CPC分类号： G11C8/18 , G11C7/1018
摘要： A burst length control circuit capable of performing read and write operations in high speed according to a burst length and a semiconductor memory device using the same includes a clock signal generating unit for generating first and second internal clock signals from a clock signal in response to a first and second burst signals, a control signal generating unit for driving in response to the first and second internal clock signals, wherein the control signal generating unit for generating first and second control signals, enable sections of the first and second control signals being controlled according to the first and second burst signals at a read operation or write operation, and a burst termination signal generating unit for generating a burst termination signal in response to the first and second burst signals. The first control signal is disabled in response to the burst termination signal.
摘要翻译：能够根据突发长度高速执行读写操作的突发长度控制电路和使用该突发长度的半导体存储器件包括：时钟信号产生单元，用于响应于时钟信号产生第一和第二内部时钟信号第一和第二突发信号，用于响应于第一和第二内部时钟信号而驱动的控制信号产生单元，其中用于产生第一和第二控制信号的控制信号产生单元使第一和第二控制信号的部分根据在读取操作或写入操作时与第一和第二突发信号相关联，以及突发终止信号产生单元，用于响应于第一和第二突发信号产生突发终止信号。第一控制信号响应于突发终止信号被禁用。

5. 发明授权

US07242636B2 Clock control circuit and semiconductor memory device including the same and input operation method of semiconductor memory device 有权
标题翻译：时钟控制电路和包括与半导体存储器件相同的输入操作方法的半导体存储器件
公开(公告)号：US07242636B2
公开(公告)日：2007-07-10
申请号：US11319550
申请日：2005-12-29
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/18
摘要： The present invention relates to a clock control circuit that can reduce power consumption in the input operation of an address signal and control signals and semiconductor memory device including the same, and an input operation method of the semiconductor memory device. The clock control circuit accordance to the present invention generates a control clock signal only when external address signals or external control signals are substantially input. Therefore, unnecessary power consumption a power noise phenomenon can be reduced.
摘要翻译：本发明涉及一种时钟控制电路，其能够降低地址信号和控制信号的输入操作以及包括其的半导体存储器件的功耗，以及半导体存储器件的输入操作方法。根据本发明的时钟控制电路仅在外部地址信号或外部控制信号基本上被输入时才产生控制时钟信号。因此，可以减少不必要的功耗电源噪声现象。

6. 发明授权

US09042189B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US09042189B2
公开(公告)日：2015-05-26
申请号：US13357133
申请日：2012-01-24
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G11C7/10 , G11C7/22
CPC分类号： G11C7/109 , G11C7/1027 , G11C7/222
摘要： A semiconductor memory device includes: a burst start signal generation unit configured to generate a first burst start signal by delaying a write pulse by a first period, generate a second burst start signal by delaying the write pulse by a second period, and selectively transmit the first or second burst start signal as a select burst start signal in response to a test signal; an input control signal generation unit configured to generate an input control signal in response to the first burst start signal; and a write command generation unit configured to generate a write driver enable signal in response to the select burst start signal.
摘要翻译：半导体存储器件包括：突发起始信号生成单元，被配置为通过将写入脉冲延迟第一周期来产生第一突发起始信号，通过将写入脉冲延迟第二周期来产生第二突发起始信号，并且选择性地发送第一或第二突发起始信号作为响应于测试信号的选择脉冲串起始信号; 输入控制信号生成单元，被配置为响应于所述第一突发起始信号而生成输入控制信号; 以及写命令生成单元，被配置为响应于所述选择脉冲串启动信号而产生写驱动器使能信号。

7. 发明授权

US08779800B2 Control signal generation circuit and sense amplifier circuit using the same 有权
标题翻译：控制信号发生电路和读出放大器电路使用相同
公开(公告)号：US08779800B2
公开(公告)日：2014-07-15
申请号：US13730292
申请日：2012-12-28
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G01R19/00
CPC分类号： H03F1/00 , G11C7/08 , G11C7/22 , G11C11/24 , G11C11/4076 , G11C11/4091 , H03H11/26
摘要： A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.
摘要翻译：控制信号发生电路包括电压检测单元，其检测外部电压的电平并产生第一和第二检测信号;以及控制信号控制单元，其响应于第一和第二检测信号延迟读出放大器使能信号，并产生第一通过第三控制信号。基于第一和第二检测信号的电平来控制第一和第二控制信号的使能周期。

8. 发明授权

US08354863B2 Control signal generation circuit and sense amplifier circuit using the same 有权
标题翻译：控制信号发生电路和读出放大器电路使用相同
公开(公告)号：US08354863B2
公开(公告)日：2013-01-15
申请号：US12459365
申请日：2009-06-29
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G01R19/00
CPC分类号： H03F1/00 , G11C7/08 , G11C7/22 , G11C11/24 , G11C11/4076 , G11C11/4091 , H03H11/26
摘要： A control signal generation circuit includes a voltage detection unit which detects a level of an external voltage and generates first and second detection signals and a control signal control unit which delays a sense amplifier enable signal in response to the first and second detection signals and generates first through third control signals. The enable period of the first and second control signals are controlled based on the levels of the first and second detection signals.
摘要翻译：控制信号发生电路包括电压检测单元，其检测外部电压的电平并产生第一和第二检测信号;以及控制信号控制单元，其响应于第一和第二检测信号延迟读出放大器使能信号，并且产生第一通过第三控制信号。基于第一和第二检测信号的电平来控制第一和第二控制信号的使能周期。

9. 发明授权

US07652940B2 Column access control apparatus having fast column access speed at read operation 失效
标题翻译：列访问控制装置在读取操作时具有快速的列访问速度
公开(公告)号：US07652940B2
公开(公告)日：2010-01-26
申请号：US12001300
申请日：2007-12-10
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G11C7/00
CPC分类号： G11C7/1018 , G11C11/408
摘要： A column access control apparatus comprises a column signal control unit for controlling a write CAS pulse signal and an internal CAS pulse signal in response to a first signal, and a column decoder for outputting a column decoding signal using an output signal of the column signal control unit and the first signal. The column signal control unit delays the internal CAS pulse signal and the write CAS pulse signal to output delayed signals when the first signal is activated.
摘要翻译：列存取控制装置包括：列信号控制单元，用于响应于第一信号控制写CAS脉冲信号和内部CAS脉冲信号;以及列解码器，用于使用列信号控制的输出信号输出列解码信号单位和第一个信号。列信号控制单元延迟内部CAS脉冲信号和写CAS脉冲信号，以在第一信号被激活时输出延迟信号。

10. 发明授权

US07336555B2 Refresh control circuit of pseudo SRAM 有权
标题翻译：刷新伪SRAM的控制电路
公开(公告)号：US07336555B2
公开(公告)日：2008-02-26
申请号：US11619855
申请日：2007-01-04
申请人： Yin Jae Lee
发明人： Yin Jae Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/40618
摘要： A refresh control circuit is provide for a pseudo SRAM that includes a plurality of banks. The refresh control circuit includes a buffer enable control unit that outputs a chip select internal control signal, and a bank selection unit that generates a single bank select signal or an all-bank select signal in response to the chip select internal control signal. The single bank select signal is enabled in an active operation to perform a refresh operation on one bank and the all-bank select signal is enabled in a standby operation to perform a refresh operation on all the banks.
摘要翻译：为包括多个存储体的伪SRAM提供刷新控制电路。刷新控制电路包括输出芯片选择内部控制信号的缓冲器使能控制单元和响应于芯片选择内部控制信号而生成单个组选择信号或全部组选择信号的存储体选择单元。在一个活动操作中使能单组选择信号以在一个存储体上执行刷新操作，并且在待机操作中启用全部存储体选择信号以对所有存储体执行刷新操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式