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1. 发明申请

US20050140423A1 CMOS exponential function generating circuit with temperature compensation technique 失效
标题翻译：具有温度补偿技术的CMOS指数函数发生电路
公开(公告)号：US20050140423A1
公开(公告)日：2005-06-30
申请号：US11004432
申请日：2004-12-03
申请人： Jong Kwon , Mun Park , Jong Kim , Won Song
发明人： Jong Kwon , Mun Park , Jong Kim , Won Song
IPC分类号： H03K3/021 , H03F3/45 , H03G7/00
CPC分类号： H03F3/45928 , H03F3/45179 , H03F3/45475 , H03F2203/45212 , H03F2203/45482 , H03F2203/45484 , H03F2203/45508 , H03G7/001
摘要： Provided is a CMOS exponential function generating circuit capable of compensating for the exponential function characteristic according to temperature variations. The exponential function generating circuit includes an voltage scaler scaling the value of an external gain control voltage signal, an exponential function generating unit generating exponential function current and voltage in response to a signal output from the voltage scaler, a reference voltage generator providing a reference voltage to the exponential function generating unit, and a temperature compensator compensating for the exponential function characteristic according to temperature variations.
摘要翻译：提供了能够根据温度变化补偿指数函数特性的CMOS指数函数发生电路。指数函数发生电路包括缩放外部增益控制电压信号的值的电压缩放器，响应于从电压调节器输出的信号产生指数函数电流和电压的指数函数产生单元，提供参考电压的参考电压发生器到指数函数产生单元，以及根据温度变化补偿指数函数特性的温度补偿器。

2. 发明申请

US20050253654A1 Active load circuit for low-voltage CMOS voltage gain amplifier with wide bandwidth and high gain characteristic 失效
标题翻译：用于具有宽带宽和高增益特性的低压CMOS电压增益放大器的有源负载电路
公开(公告)号：US20050253654A1
公开(公告)日：2005-11-17
申请号：US10846082
申请日：2004-05-14
申请人： Jong Kwon , Gyu Cho , Mun Park , Jong Kim
发明人： Jong Kwon , Gyu Cho , Mun Park , Jong Kim
IPC分类号： H03F3/45
CPC分类号： H03F3/45183 , H03F3/45179 , H03F2203/45644
摘要： Provided is an active load circuit of a voltage gain amplifier, which allows a high voltage gain with a low supply voltage operation in high-frequency range. The active load circuit includes a PMOS transistor which is connected between the amplifying unit and a power supply voltage and functions as a load element in a low frequency range; a negative feedback buffering unit which is connected to the gate of the PMOS transistor and functions as a common drain amplifier to stabilize the output voltage of the voltage gain amplifier and drive the voltage gain amplifier at a low voltage; and a capacitor which is connected to the negative feedback buffering unit and compensates for both an impedance and a frequency characteristics when the voltage gain amplifier operates in a high frequency range.
摘要翻译：提供了一种电压增益放大器的有源负载电路，其允许在高频范围内具有低电源电压操作的高电压增益。有源负载电路包括连接在放大单元和电源电压之间并用作低频范围内的负载元件的PMOS晶体管; 负反馈缓冲单元，其连接到PMOS晶体管的栅极并用作公共漏极放大器，以稳定电压增益放大器的输出电压并以低电压驱动电压增益放大器; 以及电容器，其连接到负反馈缓冲单元，并且当电压增益放大器在高频范围内工作时，补偿阻抗和频率特性两者。

3. 发明申请

US20070123176A1 Direct conversion rf front-end transceiver and its components 审中-公开
标题翻译：直接转换rf前端收发器及其组件
公开(公告)号：US20070123176A1
公开(公告)日：2007-05-31
申请号：US10572725
申请日：2004-09-21
申请人： Seon Han , Hyun Yu , Mun Park , Jong Kim
发明人： Seon Han , Hyun Yu , Mun Park , Jong Kim
IPC分类号： H04B1/40 , H04M1/00
CPC分类号： H04B1/30 , H04B1/408
摘要： Provided is an RF front-end transceiver having an oscillator for outputting a resonant frequency signal whose frequency is controlled by a frequency control signal provided from a frequency synthesizer or a base band processor; a receive amplifier for amplifying and outputting a receive RF signal; a receive mixer for mixing the receive RF signal amplified and the resonant frequency signal to convert the receive RF signal into a receive base band signal; a transmit mixer for mixing a transmit base band signal and the resonant frequency signal to convert the transmit base band signal into a transmit RF signal; and a transmit amplifier for amplifying and outputting the transmit RF signal, wherein a resonant frequency of at least one of the receive amplifier, the receive mixer, the transmit mixer and the transmit amplifier is controlled by the frequency control signal.
摘要翻译：提供一种RF前端收发器，具有用于输出频率由频率合成器或基带处理器提供的频率控制信号控制的谐振频率信号的振荡器; 用于放大和输出接收RF信号的接收放大器; 用于混合接收RF信号放大的接收混频器和谐振频率信号，以将接收RF信号转换成接收基带信号; 发射混频器，用于混合发射基带信号和谐振频率信号，以将发射基带信号转换成发射RF信号; 以及用于放大和输出发射RF信号的发射放大器，其中接收放大器，接收混频器，发射混频器和发射放大器中的至少一个的谐振频率由频率控制信号控制。

4. 发明申请

US20050122148A1 Circuit for controlling pulse width 有权
标题翻译：用于控制脉冲宽度的电路
公开(公告)号：US20050122148A1
公开(公告)日：2005-06-09
申请号：US10882600
申请日：2004-06-30
申请人： Mun Park
发明人： Mun Park
IPC分类号： G11C11/40 , G11C7/10 , H03K5/00 , H03K5/04 , H03K5/05 , H03K5/156
CPC分类号： G11C7/222 , G11C7/1048 , G11C7/1072 , G11C2207/002 , H03K5/05 , H03K5/156 , H03K2005/00071
摘要： The present invention discloses a circuit for controlling a pulse width including a frequency detection circuit for extracting an operation frequency band by receiving an external clock, delaying the external clock for a different time and comparing a frequency of the external clock with frequencies of the external clocks delayed for the different time, respectively, and outputting a plurality of mode signals according to the operation frequency band; and a pulse generation circuit for generating a pulse having its width varied by the operation frequency, by using a delay time based on the plurality of mode signals from the frequency detection circuit. As a result, the circuit for controlling the pulse width can be applied to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supporting various operation frequencies.
摘要翻译：本发明公开了一种用于控制脉冲宽度的电路，包括：频率检测电路，用于通过接收外部时钟提取操作频带，延迟外部时钟不同的时间，并将外部时钟的频率与外部时钟的频率进行比较分别延迟不同时间，并根据操作频带输出多个模式信号; 以及脉冲发生电路，用于通过使用基于来自频率检测电路的多个模式信号的延迟时间来产生具有随着工作频率变化的宽度的脉冲。结果，用于控制脉冲宽度的电路可以应用于诸如高速DDR2或DDR3的下一代标准DRAM以及用于支持各种操作频率的高速图形DRAM。

5. 发明申请

US20050122147A1 Circuit for controlling pulse width 有权
标题翻译：用于控制脉冲宽度的电路
公开(公告)号：US20050122147A1
公开(公告)日：2005-06-09
申请号：US10878770
申请日：2004-06-28
申请人： Mun Park
发明人： Mun Park
IPC分类号： G11C8/18 , G11C7/10 , G11C7/22 , H03K3/017 , H03K5/00 , H03K5/05 , H03K5/156
CPC分类号： G11C7/222 , G11C7/1048 , G11C7/22 , H03K5/05 , H03K5/156 , H03K2005/00071
摘要： Provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard DRAM such as a high speed DDR2 or DDR3 as well as a high speed graphic DRAM for supplying various CAS latencies by means of including: a mode register set for setting a plurality of CAS latencies according to an operation frequency by a command inputted from a chip set; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of CAS latencies set in the mode register set.
摘要翻译：提供了一种用于控制可以对下一代标准DRAM（例如高速DDR2或DDR3）进行调节的脉冲宽度的电路，以及用于通过包括以下方式提供各种CAS延迟的高速图形DRAM：模式寄存器用于根据从芯片组输入的命令根据操作频率设置多个CAS延迟; 以及脉冲发生电路，用于根据在模式寄存器组中设置的多个CAS延迟来使用延迟时间来产生具有可变宽度的脉冲。

6. 发明申请

US20050140445A1 Operational transconductance amplifier with DC offset elimination and low mismatch 有权
标题翻译：具有DC偏移消除和低失配的运算跨导放大器
公开(公告)号：US20050140445A1
公开(公告)日：2005-06-30
申请号：US11019765
申请日：2004-12-20
申请人： Young Kim , Mun Park
发明人： Young Kim , Mun Park
IPC分类号： H03F3/45
CPC分类号： H03F3/45188 , H03F3/45659 , H03F3/45717 , H03F2203/45356 , H03F2203/45394 , H03F2203/45574
摘要： Provided is a transconductor capable of eliminating a direct current (DC) offset component of a signal and compensating a mismatch of the signal. The transconductor includes amplifiers of simple circuit structures, and a common mode control DC offset elimination circuit. The transconductor includes a common mode control DC offset elimination circuit unit receiving input/output voltages to stabilize the current supplying and the output DC value, a first amplifier and a second amplifier reducing a mismatch in a transconductor circuit and increasing an output resistance, in order to prevent a signal distortion or a wrong operation of the circuit that is caused by the mismatch signal and unstable DC voltage.
摘要翻译：提供了能够消除信号的直流（DC）偏移分量并补偿信号失配的跨导体。跨导体包括简单电路结构的放大器和共模控制DC偏移消除电路。跨导体包括共模控制DC偏移消除电路单元，接收用于稳定电流供应和输出DC值的输入/输出电压，第一放大器和第二放大器，以减少跨导电路中的失配并增加输出电阻，按顺序以防止由失配信号和不稳定的直流电压引起的电路的信号失真或错误的操作。

7. 发明申请

US20050134329A1 Transconductor circuit for compensating the distortion of output current 失效
标题翻译：用于补偿输出电流失真的跨导电路
公开(公告)号：US20050134329A1
公开(公告)日：2005-06-23
申请号：US10941333
申请日：2004-09-14
申请人： Beaung Lee , Mun Park
发明人： Beaung Lee , Mun Park
IPC分类号： H03D1/00 , H03D7/14 , H03F1/32 , H03F3/45
CPC分类号： H03F1/3211 , H03D7/1441 , H03D7/1458 , H03D7/1491 , H03D2200/0043 , H03F3/45197
摘要： Provided is a transconductor circuit for compensating distortion of an output current without reducing the size of chips and operation speed characteristics. The transconductor circuit includes a main circuitry which is a differential pair with source degeneration and to which a predetermined input voltage is applied, an auxiliary circuitry which is connected to nodes of the main circuitry to compensate the distortion of the output current, a variable voltage supply which controls a depth or degree of a distortion compensation operation for the output current, and a current source which supplies the main circuitry with constant bias.
摘要翻译：提供了一种用于补偿输出电流的失真而不减小芯片尺寸和操作速度特性的跨导电路。跨导电路包括主电路，其是具有源极变性并且施加预定输入电压的差分对，辅助电路，连接到主电路的节点以补偿输出电流的失真，可变电压源其控制输出电流的失真补偿操作的深度或程度，以及为主电路提供恒定偏压的电流源。

8. 发明授权

US07180807B2 Semiconductor memory device having a delay circuit 有权
标题翻译：具有延迟电路的半导体存储器件
公开(公告)号：US07180807B2
公开(公告)日：2007-02-20
申请号：US10907905
申请日：2005-04-20
申请人： Mun Park
发明人： Mun Park
IPC分类号： G11C7/00
CPC分类号： G11C29/50012 , G11C11/401 , G11C11/406 , G11C11/4094 , G11C29/02 , G11C2211/4061
摘要： A semiconductor memory device having a delay circuit, the delay circuit is constructed in order for a refresh operation and a normal operation to have different delay paths such that a minimum tRAS (Active to Precharge command period) delay time of the refresh operation to which tRFC (Auto Referesh to Active/Auto Referesh command period) is applied is longer than a minimum tRAS delay time of a normal operation to which tRC (Active to Active/Auto Refresh command period) is applied. Thus, a greater noise margin is secured in tRFC in a refresh operation being the worst situation of a DRAM. Accordingly, the probability that fail can occur is reduced and the yield upon test is thus improved.
摘要翻译：一种具有延迟电路的半导体存储器件，延迟电路被构造为使得刷新操作和正常操作具有不同的延迟路径，使得tRFC的刷新操作的最小tRAS（活动到预充电命令周期）延迟时间（自动缩小到有效/自动刷新命令周期）的时间长于应用了tRC（活动/主动/自动刷新指令周期）的正常操作的最小tRAS延迟时间。因此，在作为DRAM的最坏情况的刷新操作中，在tRFC中确保更大的噪声容限。因此，可以发生故障的可能性降低，并且因此提高了测试的产量。

9. 发明申请

US20060233033A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20060233033A1
公开(公告)日：2006-10-19
申请号：US10907872
申请日：2005-04-19
申请人： Mun Park
发明人： Mun Park
IPC分类号： G11C7/00
CPC分类号： G11C11/4094 , G11C7/222 , G11C11/401 , G11C11/4076 , G11C29/56012 , G11C2029/1204
摘要： A semiconductor memory device comprises a central control circuit for receiving an operation command from an external chipset, generating an active signal for executing the operation command, and generating a precharge signal after a predetermined time, a row path control circuit for controlling a bank according to the active signal or the precharge signal of the central control circuit, and a precharge time control circuit, which is enabled according to the active signal to output an oscillation signal having a predetermined frequency, divides the oscillation signal based on a setting time from when an active operation is performed until when a precharge operation is performed, and then outputs a precharge time control signal, thereby controlling generation of the precharge signal of the central control circuit.
摘要翻译：一种半导体存储器件，包括一个中央控制电路，用于从外部芯片组接收一个操作命令，产生用于执行操作命令的有效信号，并在预定时间后产生一个预充电信号，一个行路径控制电路，用于根据中央控制电路的有效信号或预充电信号以及根据有源信号使能输出具有预定频率的振荡信号的预充电时间控制电路根据设定时间从振幅信号执行有效操作，直到执行预充电操作，然后输出预充电时间控制信号，从而控制中央控制电路的预充电信号的产生。

10. 发明申请

US20050193866A1 Cutting wheel with blank and manufacturing method thereof 审中-公开
标题翻译：具有空白的切割轮及其制造方法
公开(公告)号：US20050193866A1
公开(公告)日：2005-09-08
申请号：US11074512
申请日：2005-03-07
申请人： Jong Woo , Hwan Lee , Eung Kwon , Seo Pyun , Mun Park , Sang Lee , Jae Jeong , Shin Kim
发明人： Jong Woo , Hwan Lee , Eung Kwon , Seo Pyun , Mun Park , Sang Lee , Jae Jeong , Shin Kim
IPC分类号： B23D61/02 , B29C35/02 , B29C45/00 , B29C45/14 , B23D63/00
CPC分类号： B29C45/14344 , B23D61/026 , B29C35/02 , B29C45/0055 , B29C2045/0058 , B29K2705/00 , B29L2031/77 , Y10T29/4998 , Y10T29/49993
摘要： The present invention relates to a cutting wheel with blanks which reduces vibration and frictional noise generated when a workpiece such as stone, steel concrete, asphalt, metal, ceramic, or wood is cut, and a method for manufacturing the same. There is provided a cutting wheel of which a wheel body is formed with at least one blank. The blank is shaped in a line with a variable width, and the blank is filled with noise absorbing material. According to the present invention, the noise and vibration is considerably decreased as compared with a general plane type cutting wheel and a conventional cutting wheel with blanks. In addition, the cutting wheel with blanks according to the present invention can absorb the noise and vibration as good as the sandwich type cutting wheel, and particularly, is considerably high in strength, and is inexpensive to manufacture with ½ to ⅓ costs compared with the sandwich type cutting wheel.
摘要翻译：本发明涉及一种具有坯料的切割轮，其减少了当诸如石头，钢混凝土，沥青，金属，陶瓷或木材的工件被切割时产生的振动和摩擦噪音及其制造方法。设置有切割轮，轮子主体形成有至少一个坯料。坯料成形为具有可变宽度的线，并且坯料填充有噪声吸收材料。根据本发明，与一般平面型切割轮和具有坯料的常规切割轮相比，噪音和振动显着降低。此外，根据本发明的具有坯料的切割轮可以吸收与夹层型切割轮一样好的噪声和振动，并且特别是具有相当高的强度，并且制造成本低于1/2到1/3的成本夹心式切割轮。

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