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1. 发明申请

US20090201744A1 Method For Erasing A Flash Memory Cell Or An Array Of Such Cells Having Improved Erase Coupling Ratio 有权
标题翻译：用于擦除闪存单元的方法或者具有改善的擦除耦合比的这样的单元阵列
公开(公告)号：US20090201744A1
公开(公告)日：2009-08-13
申请号：US12027654
申请日：2008-02-07
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/16
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

2. 发明申请

US20070091688A1 Method of programming a non-volatile memory cell 有权
标题翻译：编程非易失性存储单元的方法
公开(公告)号：US20070091688A1
公开(公告)日：2007-04-26
申请号：US11255905
申请日：2005-10-20
申请人： Jonathan Pabustan , Ben Sheen
发明人： Jonathan Pabustan , Ben Sheen
IPC分类号： G11C7/10
CPC分类号： G11C16/0483 , G11C16/12 , G11C16/3459
摘要： The present invention relates to a method of programming a select non-volatile memory cell in a plurality of serially connected non-volatile memory cells with a serially connected select transistor. Each of the non-volatile memory cells has a control gate for receiving a programming voltage and the select transistor has a select gate for receiving a select voltage. The method comprises applying the programming voltage to the control gate of the select non-volatile memory cell in a program command sequence. The magnitude of the select voltage to the select gate of the select transistor within the program command sequence is then varied. The method can be applied to non-volatile cells in a NAND or NOR architecture.
摘要翻译：本发明涉及一种使用串行连接的选择晶体管对多个串行连接的非易失性存储单元中的选择非易失性存储单元进行编程的方法。每个非易失性存储单元具有用于接收编程电压的控制栅极，并且选择晶体管具有用于接收选择电压的选择栅极。该方法包括以编程命令序列将编程电压施加到选择非易失性存储单元的控制栅极。然后，改变在程序命令序列内选择晶体管的选择栅极的选择电压的大小。该方法可以应用于NAND或NOR架构中的非易失性单元。

3. 发明授权

US07974136B2 Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio 有权
标题翻译：擦除具有改善的擦除耦合比的这种单元的闪存单元或阵列的方法
公开(公告)号：US07974136B2
公开(公告)日：2011-07-05
申请号：US12645337
申请日：2009-12-22
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Der-Tsyr Fan , Yaw Wen Hu , Prateep Tuntasood
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

4. 发明授权

US07668013B2 Method for erasing a flash memory cell or an array of such cells having improved erase coupling ratio 有权
标题翻译：擦除具有改善的擦除耦合比的这种单元的闪存单元或阵列的方法
公开(公告)号：US07668013B2
公开(公告)日：2010-02-23
申请号：US12027654
申请日：2008-02-07
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/04
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与其隔离。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

5. 发明申请

US20060190762A1 Semiconductor memory and method of storing configuration data 有权
标题翻译：半导体存储器和存储配置数据的方法
公开(公告)号：US20060190762A1
公开(公告)日：2006-08-24
申请号：US11063316
申请日：2005-02-22
申请人： Chih-Chieh Wang , Jonathan Pabustan , Ben Sheen
发明人： Chih-Chieh Wang , Jonathan Pabustan , Ben Sheen
IPC分类号： G06F11/00
CPC分类号： G11C29/846 , G06F11/1008 , G11C29/02 , G11C29/027 , G11C29/028 , G11C29/44 , G11C29/70 , G11C2029/0407 , G11C2029/4402 , G11C2229/723
摘要： Redundantly repaired semiconductor memory and method in which the configuration data for the memory is stored in an area of the main memory array which is known to be free of bad bits, along with a signature code which serves as a pointer and verifies the validity of the configuration data. In one disclosed embodiment, the data is stored in a configuration memory which is divided into a plurality of areas of equal size and known starting addresses. The number of areas is greater than the number of permitted repairs, and the areas which do not contain defects are available for storing configuration data including device settings, repair information, and the like.
摘要翻译：冗余修复的半导体存储器和方法，其中用于存储器的配置数据被存储在已知没有坏位的主存储器阵列的区域中，以及用作指针的签名代码，并验证其的有效性配置数据。在一个所公开的实施例中，数据被存储在配置存储器中，该配置存储器被分成多个相同大小的区域和已知的起始地址。区域数量大于允许修理的数量，并且不存在缺陷的区域可用于存储包括设备设置，修理信息等的配置数据。

6. 发明申请

US20100157687A1 Method for Erasing a Flash Memory Cell or an Array of Such Cells Having Improved Erase Coupling Ratio 有权
标题翻译：擦除闪存单元或具有改善的擦除耦合比的这种单元阵列的方法
公开(公告)号：US20100157687A1
公开(公告)日：2010-06-24
申请号：US12645337
申请日：2009-12-22
申请人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
发明人： Geeng-Chuan Michael Chern , Ben Sheen , Jonathan Pabustan , Prateep Tuntasood , Der-Tsyr Fan , Yaw Wen Hu
IPC分类号： G11C16/06 , G11C16/16
CPC分类号： G11C16/16
摘要： A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel region between the first end and the second end. The flash memory cell has a plurality of stacked pairs of floating gates and control gates with the floating gates positioned over portions of the channel region and are insulated therefrom, and each control gate over a floating gate and insulated therefrom. The flash memory cell further has a plurality of erase gates over the channel region which are insulated therefrom, with an erase gate between each pair of stacked pair of floating gate and control gate. In a method of erasing the flash memory cell, a pulse of a first positive voltage is applied to alternating erase gates (“first alternating gates”). In addition, a ground voltage is applied to erase gates other than the first alternating gates (“second alternating gates”). In a second method to erase the flash memory cell, a pulse of a first positive voltage is applied to the first alternating gates and a negative voltage is applied to the second alternating gates and to all control gates.
摘要翻译：闪存单元是具有第一导电类型的衬底的类型，在第一端具有第二导电类型的第一区域，在第二端处具有与第一端部间隔开的第二导电类型的第二区域，在第一端和第二端之间具有通道区域。闪存单元具有多个堆叠的浮置栅极和控制栅极对，其中浮置栅极位于沟道区域的部分上方并与其绝缘，并且每个控制栅极在浮动栅极上并与之绝缘。闪速存储单元还在通道区域上具有与其绝缘的多个擦除栅极，在每对堆叠的一对浮置栅极和控制栅极之间具有擦除栅极。在擦除闪存单元的方法中，将第一正电压的脉冲施加到交替擦除栅极（“第一交替栅极”）。此外，施加接地电压以擦除除第一交流栅极（“第二交替栅极”）之外的栅极。在擦除闪存单元的第二种方法中，将第一正电压的脉冲施加到第一交流栅极，并且向第二交替栅极和所有控制栅极施加负电压。

7. 发明授权

US08385121B2 Memory adapted to program a number of bits to a memory cell and read a different number of bits from the memory cell 有权
标题翻译：存储器，其适于将多个位编程到存储器单元并从存储器单元读取不同数量的位
公开(公告)号：US08385121B2
公开(公告)日：2013-02-26
申请号：US12948952
申请日：2010-11-18
申请人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Jonathan Pabustan , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C11/5642 , G11C7/16 , G11C11/5628 , G11C16/0483 , G11C16/10 , G11C27/005 , G11C2211/5621 , G11C2211/5622 , G11C2211/5642 , G11C2216/14
摘要： A memory has a memory array with a memory cell. The memory is adapted to program a first number of bits into the memory cell. The memory is adapted to sense a second number of bits, different from the first number of bits, from the memory cell.
摘要翻译：存储器具有存储单元的存储器阵列。存储器适于将第一数量的位编程到存储器单元中。存储器适于从存储器单元感测与第一位数不同的第二数量的位。

8. 发明授权

US08169832B2 Methods of erase verification for a flash memory device 有权
标题翻译：闪存设备的擦除验证方法
公开(公告)号：US08169832B2
公开(公告)日：2012-05-01
申请号：US12909414
申请日：2010-10-21
申请人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
发明人： Vishal Sarin , Dzung Nguyen , Jonathan Pabustan , Jung Sheng Hoei , Jason Guo , William Saiki
IPC分类号： G11C11/34
CPC分类号： G11C16/344 , G11C16/0483 , G11C16/3445
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes a memory block. The memory block includes a plurality of data lines extending substantially parallel to one another, and a plurality of memory cells. One such method includes erasing the memory cells; and performing erase verification on the memory cells. The erase verification includes determining one memory cell by one memory cell whether the individual memory cells coupled to one of the data lines have been erased. The method can also include performing a re-erase operation that selectively re-erases unerased memory cells based at least partly on the result of the erase verification.
摘要翻译：公开了诸如涉及包括存储器块的闪速存储器件的方法和装置。存储块包括基本上彼此平行延伸的多条数据线，以及多个存储单元。一种这样的方法包括擦除存储器单元; 并对存储器单元执行擦除验证。擦除验证包括由一个存储器单元确定耦合到数据线之一中的各个存储器单元是否已经被擦除的一个存储器单元。该方法还可以包括执行至少部分地基于擦除验证的结果来选择性地重新擦除未故障存储器单元的重擦除操作。

9. 发明授权

US08023334B2 Program window adjust for memory cell signal line delay 有权
标题翻译：程序窗口调整存储单元信号线延迟
公开(公告)号：US08023334B2
公开(公告)日：2011-09-20
申请号：US12262405
申请日：2008-10-31
申请人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.
摘要翻译：描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调所选存储单元信号线上的位置。还公开了其他方法，装置等。

10. 发明申请

US20100110798A1 PROGRAM WINDOW ADJUST FOR MEMORY CELL SIGNAL LINE DELAY 有权
标题翻译：程序窗口调整记忆体信号线延迟
公开(公告)号：US20100110798A1
公开(公告)日：2010-05-06
申请号：US12262405
申请日：2008-10-31
申请人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
发明人： Jung-Sheng Hoei , Jonathan Pabustan , Vishal Sarin , William H. Radke , Frankie F. Roohparvar
IPC分类号： G11C16/10
CPC分类号： G11C16/26 , G11C5/063 , G11C11/5628 , G11C11/5642 , G11C16/10
摘要： A memory device and programming and/or reading process is described that compensates for memory cell signal line propagation delays, such as to increase the overall threshold voltage range and non-volatile memory cell states available. Memory cell signal line propagation delay compensation can be accomplished by characterizing the memory cell signal line propagation delay, such as determining an amount of error due to the delay, and pre-compensating the programmed threshold voltage of the memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Alternatively, memory cell signal line propagation delay can be post-compensated for, or the pre-compensation fine tuned, after sensing the threshold voltages of the selected memory cells based on the amount of error induced by the memory cell signal line propagation delay and cell location on the selected memory cell signal line. Other methods, devices, etc., are also disclosed.
摘要翻译：描述了补偿存储器单元信号线传播延迟的存储器件和编程和/或读取过程，例如增加总体阈值电压范围和可用的非易失性存储器单元状态。可以通过表征存储单元信号线传播延迟来实现存储单元信号线传播延迟补偿，例如确定由于延迟引起的误差量，并且基于误差量预先补偿存储器单元的编程阈值电压由所选存储单元信号线上的存储单元信号线传播延迟和单元位置引起。或者，可以基于由存储器单元信号线传播延迟和单元引起的误差量感测所选择的存储器单元的阈值电压之后，对存储单元信号线传播延迟进行后补偿或预补偿微调所选存储单元信号线上的位置。还公开了其他方法，装置等。

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